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11. 发明授权

US08004446B2 A/D converter and A/D conversion method 有权
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US08004446B2
公开(公告)日：2011-08-23
申请号：US12529092
申请日：2008-02-28
申请人： Toshiaki Ozeki , Koji Oka , Daisuke Nomasaki , Ikuo Hidaka , Yoshikazu Makabe
发明人： Toshiaki Ozeki , Koji Oka , Daisuke Nomasaki , Ikuo Hidaka , Yoshikazu Makabe
IPC分类号： H03M1/38
CPC分类号： H03M1/1215 , H03M1/168
摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.
摘要翻译： A / D转换器，其通过使用第一和第二流水线型单元A / D转换器对模拟输入信号执行时分并行处理，将模拟输入信号转换为数字输出信号。 A / D转换器根据系统请求设置多个单元A / D转换器，执行并行处理，使得当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器被控制信号停止，从而减少单元A / D转换器之间的通道间误差，以提高A / D转换器的精度。

12. 发明申请

US20100097136A1 A/D CONVERTER AND A/D CONVERSION METHOD 有权
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US20100097136A1
公开(公告)日：2010-04-22
申请号：US12643613
申请日：2009-12-21
申请人： Toshiaki OZEKI , Daisuke Nomasaki , Koji Oka
发明人： Toshiaki OZEKI , Daisuke Nomasaki , Koji Oka
IPC分类号： H03F3/38
CPC分类号： H03M1/168
摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.
摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

13. 发明申请

US20080158035A1 CLOCK SIGNAL GENERATING DEVICE AND ANALOG-DIGITAL CONVERSION DEVICE 有权
标题翻译：时钟信号发生装置和模拟数字转换装置
公开(公告)号：US20080158035A1
公开(公告)日：2008-07-03
申请号：US11964943
申请日：2007-12-27
申请人： Yoshikazu Makabe , Ikuo Hidaka , Koji Oka , Toshiaki Ozeki
发明人： Yoshikazu Makabe , Ikuo Hidaka , Koji Oka , Toshiaki Ozeki
IPC分类号： H03M1/12 , G06F1/04 , H03K3/356
CPC分类号： H03M1/0624 , G06F1/06 , H03K5/151 , H03M1/1215
摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.
摘要翻译：第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子到第一D输入端，并将信号输出到第一D输入端作为反馈。第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器基于时钟信号输出。第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为基于时钟信号的第二输出。第一输出和第二输出具有在相同定时反转的信号波形。

14. 发明申请

US20100117879A1 A/D CONVERTER AND A/D CONVERSION METHOD 有权
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US20100117879A1
公开(公告)日：2010-05-13
申请号：US12529092
申请日：2008-02-28
申请人： Toshiaki Ozeki , Koji Oka , Daisuke Nomasaki , Ikuo Hidaka , Yoshikazu Makabe
发明人： Toshiaki Ozeki , Koji Oka , Daisuke Nomasaki , Ikuo Hidaka , Yoshikazu Makabe
IPC分类号： H03M1/00 , H03M1/12 , H03M1/36
CPC分类号： H03M1/1215 , H03M1/168
摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.
摘要翻译：通过使用第一和第二流水线型单元A / D转换器（121,122）对模拟输入信号进行时分并行处理，将模拟输入信号转换为数字输出信号的A / D转换器具有设定多个单元 A / D转换器，其根据系统请求执行并行处理，当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器（122）通过控制信号（15），从而减少单元A / D转换器之间的通道间误差，提高A / D转换器的精度。

15. 发明授权

US07649487B2 A/D converter and A/D conversion method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US07649487B2
公开(公告)日：2010-01-19
申请号：US11631844
申请日：2006-03-24
申请人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
发明人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.
摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

16. 发明申请

US20110254125A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110254125A1
公开(公告)日：2011-10-20
申请号：US12600094
申请日：2008-05-16
申请人： Daisuke Nomasaki , Koji Oka , Toshiaki Ozeki
发明人： Daisuke Nomasaki , Koji Oka , Toshiaki Ozeki
IPC分类号： H01L27/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2224/05553 , H01L2224/06 , H01L2924/0002 , H03H11/04 , H03H2001/0014 , H03L7/0891 , H03L7/093 , H01L2924/00
摘要： A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.
摘要翻译：根据本发明的半导体集成电路配备有具有梳状电容器（10）的多个模拟宏，每个梳状电容器（10）具有梳状的第一电极（11）和梳状的第二电极（12）电极（11）的梳齿部（13）和电极（12）的梳齿部（14）接合，使得梳齿部（13）和梳齿部（14）交替平行配置并且梳状电容器的梳齿间隔S根据指示实际电容值和理想电容值之间的误差的绝对精度或指示相邻梳状电容器之间的电容值差的相对精度而变化。因此，可以提供一种半导体集成电路，其配备有高精度模拟宏和具有确保高电容精度的梳状电容器的高度集成的模拟宏。

17. 发明授权

US07609194B2 Clock signal generating device and analog-digital conversion device 有权
标题翻译：时钟信号发生装置和模拟数字转换装置
公开(公告)号：US07609194B2
公开(公告)日：2009-10-27
申请号：US11964943
申请日：2007-12-27
申请人： Yoshikazu Makabe , Ikuo Hidaka , Koji Oka , Toshiaki Ozeki
发明人： Yoshikazu Makabe , Ikuo Hidaka , Koji Oka , Toshiaki Ozeki
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , G06F1/06 , H03K5/151 , H03M1/1215
摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.
摘要翻译：第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子到第一D输入端，并将信号输出到第一D输入端作为反馈。第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器基于时钟信号输出。第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为基于时钟信号的第二输出。第一输出和第二输出具有在相同定时反转的信号波形。

18. 发明授权

US08350917B2 Digital camera, method for sending image data and system for transmitting and receiving image data 有权
标题翻译：数码相机，发送图像数据的方法和用于发送和接收图像数据的系统
公开(公告)号：US08350917B2
公开(公告)日：2013-01-08
申请号：US10658549
申请日：2003-09-10
申请人： Koji Oka , Naoki Tsunoda
发明人： Koji Oka , Naoki Tsunoda
IPC分类号： H04N5/232 , H04N5/225
CPC分类号： H04N5/23206 , H04N1/00127 , H04N2201/0039 , H04N2201/0084
摘要： A digital camera (1) which includes an external memory device (12) to store image data, a communication device (15) connected to LAN to conduct a data communication, and a control section (10) to control these. Request data is broadcast to the LAN by the camera, and when data responding to the request data is received from a device connected to the LAN, the control section detects an IP address of the equipment from which the response data is sent, and the control section (10) sends the image data to the IP address.
摘要翻译：一种数字照相机（1），其包括存储图像数据的外部存储装置（12），连接到LAN以进行数据通信的通信装置（15）以及控制部分（10）。请求数据由相机广播到LAN，当从连接到LAN的设备接收到响应请求数据的数据时，控制部分检测发送响应数据的设备的IP地址，控制部分（10）将图像数据发送到IP地址。

19. 发明授权

US07372002B2 Fluid heating device and cleaning device using the same 失效
标题翻译：流体加热装置及使用其的清洗装置
公开(公告)号：US07372002B2
公开(公告)日：2008-05-13
申请号：US10566977
申请日：2004-08-03
申请人： Kazushige Nakamura , Shigeru Shirai , Yasuhiro Umekage , Mitsuyuki Furubayashi , Koji Oka
发明人： Kazushige Nakamura , Shigeru Shirai , Yasuhiro Umekage , Mitsuyuki Furubayashi , Koji Oka
IPC分类号： H05B1/02
CPC分类号： F24H1/102 , D06F39/04 , E03D9/08
摘要： A washing water inlet for receiving washing water is provided on an upper surface at one end of a case main body in a fluid heating device, and a washing water outlet for feeding heated washing water to a pump is provided on an upper surface at the other end of the case main body. A linear sheathed heater is arranged so as to penetrate the case main body. A spring is spirally wound around an outer peripheral surface of the sheathed heater. An outer peripheral surface of the sheathed heater, the spring, and an inner peripheral surface of the case main body form a flow path. The flow path is formed in a spiral shape with the length of the case main body used as its axis.
摘要翻译：用于接收洗涤水的洗涤水入口设置在流体加热装置中的壳体主体的一端的上表面上，并且在另一个的上表面上设置用于将加热的洗涤水供给到泵的洗涤水出口机壳主体端。线性护套加热器布置成穿过壳体主体。螺旋缠绕在护套加热器的外周表面上的弹簧。护套加热器的外周面，弹簧和壳主体的内周面形成流路。流路形成为以壳体主体的长度作为其轴线的螺旋形状。

20. 发明申请

US20050001752A1 D/A converter 失效
标题翻译： D / A转换器
公开(公告)号：US20050001752A1
公开(公告)日：2005-01-06
申请号：US10864376
申请日：2004-06-10
申请人： Heiji Ikoma , Koji Oka
发明人： Heiji Ikoma , Koji Oka
IPC分类号： H03M1/10 , H03M1/66 , H03M1/74
CPC分类号： H03M1/108 , H03M1/742
摘要： A current output type D/A converter for converting a digital signal into an analog signal comprises a control signal input terminal for receiving a control signal supplied from the outside, and an output load element having a switching mechanism for electrically connecting or disconnecting the output load element to/from an analog output node on the basis of the control signal applied to the control input terminal.
摘要翻译：用于将数字信号转换为模拟信号的电流输出型D / A转换器包括用于接收从外部提供的控制信号的控制信号输入端子和具有用于电连接或断开输出负载的切换机构的输出负载元件基于施加到控制输入端子的控制信号，来自/来自模拟输出节点的元件。

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