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11. 发明授权

US07941278B2 MicroRNA motifs 有权
标题翻译：微RNA图案
公开(公告)号：US07941278B2
公开(公告)日：2011-05-10
申请号：US11617038
申请日：2006-12-28
申请人： Yu-Ching Chang , Yu-Yu Lin , Shiu-Chieh Lan , Cheng-Tao Wu , Chung-Cheng Liu
发明人： Yu-Ching Chang , Yu-Yu Lin , Shiu-Chieh Lan , Cheng-Tao Wu , Chung-Cheng Liu
IPC分类号： G06F7/00
CPC分类号： C12N15/111 , C12N2310/14 , C12N2320/11 , C12N2330/10 , G06F19/16 , G06F19/18 , G06F19/22
摘要： Disclosed are methods of identifying microRNA motifs or microRNA precursors for a target gene or a set of target genes. Also disclosed are related computer-readable media.
摘要翻译：公开了鉴定靶基因或一组靶基因的微小RNA基序或微小RNA前体的方法。还公开了相关的计算机可读介质。

12. 发明授权

US08824188B2 Operating method for memory device and memory array and operating method for the same 有权
标题翻译：存储器件和存储器阵列的操作方法和操作方法相同
公开(公告)号：US08824188B2
公开(公告)日：2014-09-02
申请号：US13567750
申请日：2012-08-06
申请人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
发明人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/004 , G11C2013/0047 , G11C2013/0052 , G11C2013/0073 , G11C2213/77
摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.
摘要翻译：提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。存储器件的操作方法包括以下步骤。使存储器件处于置位状态。用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。读取设置状态的存储器件。一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。将恢复的偏置电压施加到存储器件。在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

13. 发明申请

US20130015234A1 Method of Forming a Package Substrate 审中-公开
标题翻译：形成封装基板的方法
公开(公告)号：US20130015234A1
公开(公告)日：2013-01-17
申请号：US13620225
申请日：2012-09-14
申请人： Chin-Sung Lin , Li-Hua Lin , Yu-Yu Lin
发明人： Chin-Sung Lin , Li-Hua Lin , Yu-Yu Lin
IPC分类号： H05K3/00 , H05K13/04
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/29 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/85444 , H01L2224/85455 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/078 , H01L2924/14 , H01L2924/3011 , H05K1/0253 , H05K3/3436 , Y10T156/1089 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要： In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.
摘要翻译：根据实施例，一种方法包括在其上提供具有导电材料的基板，从导电材料形成接地平面，第一迹线轨道和第一垂直迹线，以及在接地平面上形成绝缘体材料，第一轨迹轨迹和第一条垂直轨迹。接地平面位于第一轨迹和衬底的区域之间，在该区域上将是模具。第一轨迹沿接地平面的第一外边缘延伸，并且第一垂直迹线耦合到第一迹线轨道并且从第一轨迹线垂直延伸。

14. 发明申请

US20120018884A1 Semiconductor package structure and forming method thereof 审中-公开
标题翻译：半导体封装结构及其形成方法
公开(公告)号：US20120018884A1
公开(公告)日：2012-01-26
申请号：US12923461
申请日：2010-09-23
申请人： Yu-Yu Lin , Li-Hua Lin , Chung-Kai Wang
发明人： Yu-Yu Lin , Li-Hua Lin , Chung-Kai Wang
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/3107 , H01L23/3121 , H01L23/3135 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/451 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/00015 , H01L2224/05599
摘要： The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having an active surface and back surface, a plurality of pads on the active surface, and the chip is attached on the top surface of the substrate; a plurality of wires is electrically connected the plurality of pads on the active surface of the chip with the plurality of first connecting points on the top surface of substrate; a first encapsulant is filled to cover portion of the plurality of wires, the chip, and the portion of top surface of the substrate; a second encapsulate is filled to cover the first encapsulant, the plurality of wires and is formed on portion of the top surface of the substrate, in which the Yang's module of the second encapsulant is different with that of the first encapsulant; and a plurality of connecting components is disposed on the back surface of the substrate and is electrically connected the plurality of second connecting points.
摘要翻译：本发明提供一种半导体封装结构，其包括具有上表面和背面的基板，顶面上的多个第一连接点和背面上的多个第二连接点; 具有活性表面和背面的芯片，有源表面上的多个焊盘，并且所述芯片附接在所述衬底的顶表面上; 多个导线将芯片的有效表面上的多个焊盘与衬底的顶表面上的多个第一连接点电连接; 第一密封剂被填充以覆盖多个电线的部分，芯片和衬底的顶表面的部分; 填充第二封装以覆盖第一密封剂，多根导线并形成在基板的顶表面的部分上，其中第二密封剂的杨氏模块与第一密封剂的杨氏模块不同; 并且多个连接部件设置在基板的背面上并与多个第二连接点电连接。

15. 发明申请

US20120000763A1 SEAWATER DESALINATION DEVICE 审中-公开
标题翻译：海水淡化装置
公开(公告)号：US20120000763A1
公开(公告)日：2012-01-05
申请号：US12856335
申请日：2010-08-13
申请人： Chun-Feng Lee , Yu-Yu Lin , Tsung-Ching Chen
发明人： Chun-Feng Lee , Yu-Yu Lin , Tsung-Ching Chen
IPC分类号： B01D1/00 , C02F9/02
CPC分类号： C02F1/048 , B01D61/00 , B01D61/36 , B01D63/082 , B01D71/36 , B01D2311/04 , Y02A20/128 , Y02A20/131 , B01D2311/2673
摘要： A seawater desalination device includes a seawater reservoir having a bottom wall and adapted for holding seawater, an evaporator adapted for evaporating the seawater held in the seawater reservoir into water vapor, osmosis membrane modules installed in the seawater reservoir and spaced above the bottom wall of the seawater reservoir, each osmosis membrane having membranes for the passing of the water vapor evaporated by the evaporator and a water vapor accumulation chamber surrounded by the membranes and a suction pipe connected to the water vapor accumulation chamber, and a pump unit having a pipe connected to the suction pipe of each osmosis membrane module and adapted for drawing water vapor out of the water vapor accumulation chamber of each osmosis membrane module.
摘要翻译：海水淡化装置包括具有底壁并用于容纳海水的海水储存器，适于将保持在海水储存器中的海水蒸发成水蒸气的蒸发器，安装在海水储存器中的隔离膜模块，并在每个渗透膜具有用于使由蒸发器蒸发的水蒸气通过的膜和由膜围绕的水蒸汽积聚室和连接到水蒸气聚积室的抽吸管，以及泵单元，其具有连接到每个渗透膜组件的吸管，用于将水蒸气从每个渗透膜组件的水蒸汽积聚室中抽出。

16. 发明申请

US20080164620A1 MULTI-CHIP PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：多芯片包装及其制造方法
公开(公告)号：US20080164620A1
公开(公告)日：2008-07-10
申请号：US11679666
申请日：2007-02-27
申请人： Yu-Yu Lin , Tsrong-Yi Wen
发明人： Yu-Yu Lin , Tsrong-Yi Wen
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L23/3121 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/13099 , H01L2224/14 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip package including a carrier, at least one first chip, and a second chip is provided. The first chip is electrically connected to the carrier and disposed on the carrier. The second chip is electrically connected to the first chip and the carrier. A part of the second chip is disposed on the first chip and another part of the second chip is disposed on the carrier. A method of fabricating the multi-chip package is also provided.
摘要翻译：提供了包括载体，至少一个第一芯片和第二芯片的多芯片封装。第一芯片电连接到载体并设置在载体上。第二芯片电连接到第一芯片和载体。第二芯片的一部分设置在第一芯片上，而第二芯片的另一部分设置在载体上。还提供了一种制造多芯片封装的方法。

17. 发明申请

US20070275392A1 MicroRNA motifs 有权
标题翻译：微RNA图案
公开(公告)号：US20070275392A1
公开(公告)日：2007-11-29
申请号：US11617038
申请日：2006-12-28
申请人： Yu-Ching Chang , Yu-Yu Lin , Shiu-Chieh Lan , Cheng-Tao Wu , Chung-Cheng Liu
发明人： Yu-Ching Chang , Yu-Yu Lin , Shiu-Chieh Lan , Cheng-Tao Wu , Chung-Cheng Liu
IPC分类号： C12Q1/68
CPC分类号： C12N15/111 , C12N2310/14 , C12N2320/11 , C12N2330/10 , G06F19/16 , G06F19/18 , G06F19/22
摘要： Disclosed are methods of identifying microRNA motifs or microRNA precursors for a target gene or a set of target genes. Also disclosed are related computer-readable media.
摘要翻译：公开了鉴定靶基因或一组靶基因的微小RNA基序或微小RNA前体的方法。还公开了相关的计算机可读介质。

18. 发明授权

US06287896B1 Method for manufacturing lead frames and lead frame material for semiconductor device 有权
标题翻译：半导体器件引线框架和引线框架材料的制造方法
公开(公告)号：US06287896B1
公开(公告)日：2001-09-11
申请号：US09396494
申请日：1999-09-13
申请人： Shinn-Horng Yeh , Shu-Chin Chou , Ya-Ru Huang , Yu-Yu Lin
发明人： Shinn-Horng Yeh , Shu-Chin Chou , Ya-Ru Huang , Yu-Yu Lin
IPC分类号： H01L23/495 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49582 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48664 , H01L2224/73265 , H01L2224/85464 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The present invention is related to a method for manufacturing lead frames and a lead frame material including an intermediate layer and a top layer. The intermediate layer is composed of a layer of nickel-cobalt alloy having 5 to 30 wt. % of cobalt and a thickness of 3 to 20 microinches and a layer of nickel or nickel alloy having a thickness of 10 to 80 microinches. The intermediate layer can inhibit the diffusion of the base metal to the surface of the leads. The top layer consisting of gold or gold alloy, which is composed of gold and at least one metal selected from the group consisting of palladium, silver, tin and copper and has at least 60 weight percent gold, has a thickness of 0.1 to 5 microinches.
摘要翻译：本发明涉及一种用于制造引线框架的方法和包括中间层和顶层的引线框架材料。中间层由具有5〜30重量％的镍钴合金层构成。钴，厚度为3至20微英寸，厚度为10至80微英寸的镍或镍合金层。中间层可以抑制基体金属到引线表面的扩散。由金和金合金组成的顶层由金和至少一种选自钯，银，锡和铜的金属组成，并且具有至少60重量％的金，其厚度为0.1至5微英寸。

19. 发明授权

US09117515B2 Programmable metallization cell with two dielectric layers 有权
标题翻译：具有两个电介质层的可编程金属化电池
公开(公告)号：US09117515B2
公开(公告)日：2015-08-25
申请号：US13352946
申请日：2012-01-18
申请人： Feng-Ming Lee , Yu-Yu Lin
发明人： Feng-Ming Lee , Yu-Yu Lin
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00 , H01L27/24 , G11C8/10
CPC分类号： G11C13/0011 , G11C8/10 , G11C2213/54 , G11C2213/71 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1675
摘要： A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.
摘要翻译：可编程金属化器件包括第一电极和第二电极，以及在第一和第二电极之间串联的第一电介质层，第二电介质层和离子供给层。在操作中，在第一电介质层中形成或破坏导电桥以表示数据值。在读取期间，施加足以在第二电介质层中形成瞬态电桥的读取偏压，并且如果桥存在于第一介电层中，则形成通过电池的导电路径。如果在读取期间桥不在第一电介质层中，则不形成导电路径。在去除读取的偏置电压时，形成在第二介电层中的任何导电桥被破坏，而相应的其它第一介电层（如果有的话）中的导电桥保留。

20. 发明申请

US20130182487A1 PROGRAMMABLE METALLIZATION CELL WITH TWO DIELECTRIC LAYERS 有权
标题翻译：具有两个介电层的可编程金属化电池
公开(公告)号：US20130182487A1
公开(公告)日：2013-07-18
申请号：US13352946
申请日：2012-01-18
申请人： FENG-MING LEE , Yu-Yu Lin
发明人： FENG-MING LEE , Yu-Yu Lin
IPC分类号： G11C11/00 , H01L21/822 , H01L27/08
CPC分类号： G11C13/0011 , G11C8/10 , G11C2213/54 , G11C2213/71 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1675
摘要： A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.
摘要翻译：可编程金属化器件包括第一电极和第二电极，以及在第一和第二电极之间串联的第一电介质层，第二电介质层和离子供给层。在操作中，在第一电介质层中形成或破坏导电桥以表示数据值。在读取期间，施加足以在第二电介质层中形成瞬态电桥的读取偏压，并且如果桥存在于第一介电层中，则形成通过电池的导电路径。如果在读取期间桥不在第一电介质层中，则不形成导电路径。在去除读取的偏置电压时，形成在第二介电层中的任何导电桥被破坏，而相应的其它第一介电层（如果有的话）中的导电桥保留。

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