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11. 发明授权

US5926234A Liquid crystal display device 失效
标题翻译：液晶显示装置
公开(公告)号：US5926234A
公开(公告)日：1999-07-20
申请号：US877567
申请日：1997-06-17
申请人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
发明人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1362 , G02F1/1368 , G09G3/36 , H01L29/78 , H01L29/786 , G02F1/1333 , G02F1/1345 , H01L23/62
CPC分类号： G02F1/13454 , G02F1/136204 , G02F2001/136254 , G09G3/3611 , H01L2924/0002
摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
摘要翻译：用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。当形成驱动电路时，保护电路同时形成在绝缘基板上。在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。

12. 发明授权

US07196699B1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US07196699B1
公开(公告)日：2007-03-27
申请号：US09506033
申请日：2000-02-16
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00 , G09G3/26 , H03K19/0175 , H03K19/00 , H03K5/153
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

13. 发明申请

US20050057556A1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

14. 发明授权

US5977944A Data signal output circuit for an image display device 失效
标题翻译：用于图像显示装置的数据信号输出电路
公开(公告)号：US5977944A
公开(公告)日：1999-11-02
申请号：US909481
申请日：1997-08-11
申请人： Yasushi Kubota , Kenichi Katoh , Ichiro Shiraki
发明人： Yasushi Kubota , Kenichi Katoh , Ichiro Shiraki
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C19/00 , H03K17/00
CPC分类号： G09G3/3688 , G09G3/3648 , G09G3/2074
摘要： A data signal output circuit is divided into a plurality of blocks, each having its own supply circuit. In each block, a plurality of shift register sections, constituting a shift register, output pulse signals which have been shifted according to clock signals. Driving sections sample a digital image signal in synchronism with the pulse signal, and output data signals corresponding to the image signal thus sampled to a plurality of output lines. Each supply circuit provided in the blocks receives the image signal when the image signal should be sampled by the driving sections, thereby supplying the image signal only to the minimum number of blocks to be operated. In this manner, the image signal is selectively supplied to the block so as to reduce the effective load on the image signal. As a result, the power consumption generated in the image signal lines can be reduced.
摘要翻译：数据信号输出电路被分成多个块，每个块具有其自己的供电电路。在每个块中，构成移位寄存器的多个移位寄存器部分输出根据时钟信号被移位的脉冲信号。驱动部分与脉冲信号同步地采样数字图像信号，并且将与所采样的图像信号对应的数据信号输出到多条输出线。当图像信号被驱动部分采样时，在块中提供的每个供给电路接收图像信号，从而仅将图像信号提供给要被操作的最小数量的块。以这种方式，图像信号被选择性地提供给块，以便减小对图像信号的有效负载。结果，可以减少图像信号线中产生的功率消耗。

15. 发明授权

US5926156A Matrix type image display using backup circuitry 失效
标题翻译：使用备用电路的矩阵型图像显示
公开(公告)号：US5926156A
公开(公告)日：1999-07-20
申请号：US556140
申请日：1995-11-09
申请人： Kenichi Katoh , Yasushi Kubota , Hiroshi Yoneda , Osamu Sasaki , Ichiro Shiraki
发明人： Kenichi Katoh , Yasushi Kubota , Hiroshi Yoneda , Osamu Sasaki , Ichiro Shiraki
IPC分类号： G09G3/36 , G02F1/136
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2330/08
摘要： A driving circuit in a matrix type image display apparatus including a plurality of groups each including four standard unit circuits and one backup unit circuit. Each standard unit circuit includes disconnecting means for isolating the standard unit circuit from the driving circuit, and the backup unit circuit includes connecting means for connecting the backup unit circuit to an input signal line and an output signal line of any of the standard unit circuits within a group. The number of the backup unit circuits can be changed in accordance with a conforming ratio of each unit circuit, which makes it possible to eliminate idle backup unit circuits while maintaining a high overall conforming ratio of the driving circuit, thereby enhancing manufacturing efficiencies and reducing manufacturing costs.
摘要翻译：一种矩阵型图像显示装置中的驱动电路，包括多个组，每组包括四个标准单元电路和一个备用单元电路。每个标准单元电路包括用于将标准单元电路与驱动电路隔离的断开装置，并且备用单元电路包括用于将备用单元电路连接到任何标准单元电路的输入信号线和输出信号线的连接装置一个小组。备用单元电路的数量可以根据每个单元电路的一致比例而改变，这使得可以在保持驱动电路的高整体比例的同时消除空闲备用单元电路，从而提高制造效率并减少制造费用

16. 发明授权

US5844538A Active matrix-type image display apparatus controlling writing of display data with respect to picture elements 失效
标题翻译：有源矩阵型图像显示装置控制对图像元素的显示数据的写入
公开(公告)号：US5844538A
公开(公告)日：1998-12-01
申请号：US363218
申请日：1994-12-23
申请人： Ichiro Shiraki , Manabu Matsuura , Yasushi Kubota , Hiroshi Yoneda , Yoshitaka Yamamoto
发明人： Ichiro Shiraki , Manabu Matsuura , Yasushi Kubota , Hiroshi Yoneda , Yoshitaka Yamamoto
IPC分类号： G09G3/36 , G09G5/399
CPC分类号： G09G3/3648 , G09G2300/0814 , G09G2300/0842 , G09G2310/0235 , G09G2320/0219 , G09G2320/0247 , G09G3/3659 , G09G3/3666 , G09G5/399
摘要： An image display apparatus can be arranged so that a picture element capacity obtains a value provides display data retention of less than 99% by writing same data to a picture element a plurality of times during 1 frame period. This makes it possible to disuse the auxiliary capacity and to improve an aperture ratio. Moreover, with the present invention, an MOS transistor arranged in each picture element as a switching element for driving the picture element, a scan signal line driving circuit and a data signal line driving circuit for transmitting a driving signal based upon display data to the MOS transistor through a data signal line and a scan signal line, and a first frame memory and a second frame memory provided outside the picture element for storing display data to be outputted to a data signal line driving circuit for 1 frame are formed on one substrate. As a result, it is possible to improve package efficiency and lower cost by using a driver monolithic technique.
摘要翻译：图像显示装置可以被布置为使得通过在1帧周期期间将相同的数据多次写入到图像元素中，图像元素容量获得提供小于99％的显示数据保持。这使得可以消除辅助容量并提高开口率。此外，根据本发明，配置在每个像素中的MOS晶体管作为用于驱动像素的开关元件，扫描信号线驱动电路和数据信号线驱动电路，用于根据显示数据向MOS发送驱动信号晶体管通过数据信号线和扫描信号线，并且在一个基板上形成用于存储要输出到1帧的数据信号线驱动电路的显示数据的图像元件外部的第一帧存储器和第二帧存储器。结果，可以通过使用驱动器单片技术来提高封装效率和降低成本。

17. 发明授权

US06580411B1 Latch circuit, shift register circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路和图像显示设备以低功耗运行
公开(公告)号：US06580411B1
公开(公告)日：2003-06-17
申请号：US09300178
申请日：1999-04-27
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G336
CPC分类号： H03K3/356121 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0257 , G09G2330/021 , H03K3/356139
摘要： If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.
摘要翻译：如果时钟信号ck为“H”，并且（第一控制信号）中的输入脉冲信号为“H”，则n型晶体管M15和M16导通，使输出节点/ OUT具有GND电平。然后，p型晶体管M12导通，使得输出节点OUT具有Vcc（16V）电平。因此，当第一和第二控制信号和时钟信号ck处于“H”时，锁存电路LAT作为电平移位器电路工作，并且在任何其它情况下作为电平保持电路工作。因此，由锁存电路LAT构成的移位寄存器电路用作低电压接口，并且当锁存电路LAT不活动时，时钟信号ck的输入停止，使得时钟的负载和功率的消耗信号线减少。

18. 发明授权

US06225866B1 Series connected multi-stage linear FET amplifier circuit 失效
标题翻译：串联多级线性FET放大电路
公开(公告)号：US06225866B1
公开(公告)日：2001-05-01
申请号：US09594439
申请日：2000-06-14
申请人： Yasushi Kubota , Ichiro Shiraki
发明人： Yasushi Kubota , Ichiro Shiraki
IPC分类号： H03F368
CPC分类号： G09G3/3688 , H03F3/345
摘要： A sampling circuit is arranged so that source voltages VDD and VEE, which are to be applied to two inverters at the latter stages in a signal path on the p-channel transistor side, are shifted to the positive side with respect to source voltages VCC and VSS that are applied to the other inverters. With such a power supply construction, video signals on the low-potential side in a video signal line are picked up by the n-channel transistor and video signals on the high-potential side are picked up by the p-channel transistor, and the resulting signals are supplied to a data signal line. This arrangement makes it possible to reduce the gate input voltage upon conduction of the sampling switch. Moreover, by shifting the levels of the source voltages as described above, it becomes possible to ensure writing and holding operations even in the case of having signals with a small amplitude. Therefore, even in the case when devices having low withstand voltage are used, no damage is caused on the circuit characteristics.
摘要翻译：采样电路被布置成使得要施加到p沟道晶体管侧的信号路径中的后级的两个反相器的源极电压VDD和VEE相对于源极电压VCC和 VSS应用于其他逆变器。通过这样的电源结构，视频信号线的低电位侧的视频信号由n沟道晶体管拾取，高电位侧的视频信号被p沟道晶体管拾取，产生的信号被提供给数据信号线。这种布置使得可以在采样开关导通时降低栅极输入电压。此外，通过如上所述移动源电压的电平，即使在具有小幅度的信号的情况下也可以确保写入和保持操作。因此，即使在使用耐压低的装置的情况下，也不会对电路特性造成损害。

19. 发明授权

US5754155A Image display device 失效
标题翻译：图像显示装置
公开(公告)号：US5754155A
公开(公告)日：1998-05-19
申请号：US591281
申请日：1996-01-25
申请人： Yasushi Kubota , Ichiro Shiraki
发明人： Yasushi Kubota , Ichiro Shiraki
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G3/3696 , G09G2300/0408 , G09G2320/041 , G09G2330/02 , G09G3/2011
摘要： In an image display device, a reference voltage generating circuit of a power supply circuit, which applies power supply voltages V.sub.GH and V.sub.GL to a scan signal line driving circuit, is formed on a substrate where picture elements for display are formed, and a transistor which composes the reference voltage generating circuit has the approximately same threshold voltage as a picture element transistor TR.sub.(PIX) which composes the picture elements for display. As a result, the power supply voltages V.sub.GH and V.sub.GL to the scan signal line driving circuit automatically obtain which is optimized for a characteristic of the transistor TR(PIX) which composes the picture elements for display. Therefore, the power supply voltages V.sub.GH and V.sub.GL do not require adjustment per picture element array or every time when the usage environment is changed. As a result, the cost of adjustment is reduced and convenience of the usage is improved.
摘要翻译：在图像显示装置中，在扫描信号线驱动电路上施加电源电压VGH，VGL的电源电路的基准电压产生电路形成在形成有显示用象素的基板上，组成参考电压产生电路具有与组成用于显示的像素的像素晶体管TR（PIX）大致相同的阈值电压。结果，扫描信号线驱动电路的电源电压VGH和VGL自动获得针对组成用于显示的像素的晶体管TR（PIX）的特性而被优化。因此，电源电压VGH和VGL不需要对每个图像元素阵列进行调整，或者每当使用环境改变时。结果，降低了调整成本，提高了使用的便利性。

20. 发明授权

US5671026A Liquid crystal display device with TFT ESD protective devices between I/O terminals or with a short circuited alignment film 失效
标题翻译：具有I / O端子之间的TFT ESD保护装置或短路对准膜的液晶显示装置
公开(公告)号：US5671026A
公开(公告)日：1997-09-23
申请号：US394626
申请日：1995-02-27
申请人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
发明人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1362 , G02F1/1368 , G09G3/36 , H01L29/78 , H01L29/786 , G02F1/1333 , G02F1/1337 , H01L23/62
CPC分类号： G02F1/13454 , G02F1/136204 , G02F2001/136254 , G09G3/3611 , H01L2924/0002
摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
摘要翻译：用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。当形成驱动电路时，保护电路同时形成在绝缘基板上。在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。

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