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11. 发明授权

US07623379B2 Semiconductor integrated circuit device and non-volatile memory system using the same 有权
标题翻译：半导体集成电路器件和使用其的非易失性存储器系统
公开(公告)号：US07623379B2
公开(公告)日：2009-11-24
申请号：US11685391
申请日：2007-03-13
申请人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
发明人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/349
摘要： A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.
摘要翻译：半导体集成电路装置包括具有将通过作为状态返回的伪通函数的非易失性存储器，即使在完成了写入或擦除序列中的至少一个之后发生达到允许的位数的位错误。非易失性存储器包括用于控制发出伪通函数的定时的发行定时控制部分。

12. 发明授权

US07203091B2 Semiconductor integrated circuit device and non-volatile memory system using the same 有权
标题翻译：半导体集成电路器件和使用其的非易失性存储器系统
公开(公告)号：US07203091B2
公开(公告)日：2007-04-10
申请号：US11097300
申请日：2005-04-04
申请人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
发明人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
IPC分类号： G11C7/00 , G11C29/00 , G11C16/06 , G06F11/00
CPC分类号： G11C16/349
摘要： A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.
摘要翻译：半导体集成电路装置包括具有将通过作为状态返回的伪通函数的非易失性存储器，即使在完成了写入或擦除序列中的至少一个之后发生达到允许的位数的位错误。非易失性存储器包括用于控制发出伪通函数的定时的发行定时控制部分。

13. 发明申请

US20060117214A1 Non-volatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US20060117214A1
公开(公告)日：2006-06-01
申请号：US11097188
申请日：2005-04-04
申请人： Yoshihisa Sugiura , Tatsuya Tanaka , Atsushi Inoue
发明人： Yoshihisa Sugiura , Tatsuya Tanaka , Atsushi Inoue
IPC分类号： G06F11/00
CPC分类号： G11C29/52 , G06F11/1068 , G11C29/832 , G11C2029/0411
摘要： A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.
摘要翻译：非易失性存储器系统包括非易失性存储器和控制非易失性存储器的存储器控制器。即使在写入或擦除序列中的至少一个完成之后发生达到允许的位数的比特错误，非易失性存储器具有返回通过作为状态的伪通函数。存储器控制器具有改变允许位数的上限值的允许位改变功能。

14. 发明申请

US20050213390A1 Non-volatile semiconductor memory 失效
公开(公告)号：US20050213390A1
公开(公告)日：2005-09-29
申请号：US11143709
申请日：2005-06-03
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C27/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.

15. 发明申请

US20050047207A1 Non-volatile semiconductor memory 失效
公开(公告)号：US20050047207A1
公开(公告)日：2005-03-03
申请号：US10957697
申请日：2004-10-05
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C27/00 , G11C11/34
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.

16. 外观设计

USD715082S1 Pipe of a stand for supporting an instrument 有权
标题翻译：用于支撑仪器的支架管
公开(公告)号：USD715082S1
公开(公告)日：2014-10-14
申请号：US29427184
申请日：2012-07-16
申请人： Yoshihisa Sugiura
设计人： Yoshihisa Sugiura

17. 外观设计

USD711731S1 Clamp of a stand for supporting an instrument 有权
标题翻译：夹持支架的支架
公开(公告)号：USD711731S1
公开(公告)日：2014-08-26
申请号：US29427168
申请日：2012-07-16
申请人： Yoshihisa Sugiura
设计人： Yoshihisa Sugiura

18. 发明授权

US07434111B2 Non-volatile memory system having a pseudo pass function 有权
标题翻译：具有伪通函数的非易失性存储器系统
公开(公告)号：US07434111B2
公开(公告)日：2008-10-07
申请号：US11097188
申请日：2005-04-04
申请人： Yoshihisa Sugiura , Tatsuya Tanaka , Atsushi Inoue
发明人： Yoshihisa Sugiura , Tatsuya Tanaka , Atsushi Inoue
IPC分类号： G06F11/00
CPC分类号： G11C29/52 , G06F11/1068 , G11C29/832 , G11C2029/0411
摘要： A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.
摘要翻译：非易失性存储器系统包括非易失性存储器和控制非易失性存储器的存储器控制器。即使在写入或擦除序列中的至少一个完成之后发生达到允许的位数的比特错误，非易失性存储器具有返回通过作为状态的伪通函数。存储器控制器具有改变允许位数的上限值的允许位改变功能。

19. 发明授权

US07277323B2 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07277323B2
公开(公告)日：2007-10-02
申请号：US11143709
申请日：2005-06-03
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
摘要翻译：公开了一种非易失性半导体存储器，其包括多个存储单元阵列，每个存储单元阵列具有分配给相应单元阵列的一部分的重写数量的存储区域，以及存储重写数量的写入控制电路通过以比普通写入电压低的电压执行数据写入到单元晶体管，在多个存储单元阵列的未选择的存储单元阵列中重写存储区域数量的单元晶体管中的重写次数，以便根据注入到单元晶体管的浮置栅极的电子量，以模拟方式改变单元晶体管的阈值。

20. 发明授权

US06914816B2 Non-volatile semiconductor memory 失效
公开(公告)号：US06914816B2
公开(公告)日：2005-07-05
申请号：US10957697
申请日：2004-10-05
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C27/00 , G11C16/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.

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