专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07244984B2 Nonvolatile semiconductor memory including two memory cell columns sharing a single bit line 失效
标题翻译：包括共享单个位线的两个存储单元列的非易失性半导体存储器
公开(公告)号：US07244984B2
公开(公告)日：2007-07-17
申请号：US10892445
申请日：2004-07-16
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
摘要翻译：该非易失性半导体存储器包括：具有与浮动栅极串联连接的存储单元晶体管的第一和第二存储单元列以及位于该浮置栅极两侧的第一和第二控制栅极; 连接在第一存储单元列和位线之间的第一选择栅晶体管; 连接在第二存储单元列和位线之间的第二选择栅晶体管; 以及分别连接在第一存储单元列和源极线之间以及第二存储单元列和源极线之间的第三选择栅极晶体管。

12. 发明申请

US20050073001A1 Nonvolatile semiconductor memory and fabrication method therefor 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050073001A1
公开(公告)日：2005-04-07
申请号：US10892445
申请日：2004-07-16
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
摘要翻译：该非易失性半导体存储器包括：具有与浮动栅极串联连接的存储单元晶体管的第一和第二存储单元列以及位于该浮置栅极两侧的第一和第二控制栅极; 连接在第一存储单元列和位线之间的第一选择栅晶体管; 连接在第二存储单元列和位线之间的第二选择栅晶体管; 以及分别连接在第一存储单元列和源极线之间以及第二存储单元列和源极线之间的第三选择栅极晶体管。

13. 发明授权

US08377814B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08377814B2
公开(公告)日：2013-02-19
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

14. 发明授权

US08120092B2 Semiconductor memory device and manufacturing method therefor 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08120092B2
公开(公告)日：2012-02-21
申请号：US12565181
申请日：2009-09-23
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

15. 发明申请

US20100052017A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100052017A1
公开(公告)日：2010-03-04
申请号：US12553496
申请日：2009-09-03
申请人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L29/66 , H01L21/4763
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

16. 发明授权

US07505312B2 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers 有权
标题翻译：能够通过相邻电荷存储层之间的耦合来控制邻近效应的非易失性半导体存储器件
公开(公告)号：US07505312B2
公开(公告)日：2009-03-17
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

17. 发明授权

US07122430B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US07122430B2
公开(公告)日：2006-10-17
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01I21/336 , H01I21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

18. 发明申请

US20120037976A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20120037976A1
公开(公告)日：2012-02-16
申请号：US13235948
申请日：2011-09-19
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/105
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

19. 发明申请

US20110250744A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110250744A1
公开(公告)日：2011-10-13
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

20. 发明申请

US20110249493A1 NAND FLASH MEMORY 失效
标题翻译： NAND闪存
公开(公告)号：US20110249493A1
公开(公告)日：2011-10-13
申请号：US13164486
申请日：2011-06-20
申请人： Atsuhiro SATO , Fumitaka Arai
发明人： Atsuhiro SATO , Fumitaka Arai
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式