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11. 发明授权

US08011952B1 Connector assembly with card reader 有权
标题翻译：带读卡器的连接器总成
公开(公告)号：US08011952B1
公开(公告)日：2011-09-06
申请号：US12872147
申请日：2010-08-31
申请人： Yan Zhong , Jun-Jie Zheng , Xin Ji , Wen-Hsiang Hung
发明人： Yan Zhong , Jun-Jie Zheng , Xin Ji , Wen-Hsiang Hung
IPC分类号： H01R13/60
CPC分类号： H01R13/447 , H01R13/506
摘要： A connector assembly includes a connector, a card reader, and a housing. The housing includes a top cover and a bottom cover. The top cover includes a first receiving portion for the connector and a second receiving portion for the card reader. The top cover includes a baseboard fixed on the first receiving portion and a shutter moveably positioned on the second receiving portion covering the card reader.
摘要翻译：连接器组件包括连接器，读卡器和外壳。壳体包括顶盖和底盖。顶盖包括用于连接器的第一接收部分和用于读卡器的第二接收部分。顶盖包括固定在第一接收部分上的底板和可移动地定位在覆盖读卡器的第二接收部分上的挡板。

12. 发明申请

US20080276151A1 METHOD AND APPARATUS FOR DECODING A LDPC CODE 失效
标题翻译：用于解码LDPC码的方法和装置
公开(公告)号：US20080276151A1
公开(公告)日：2008-11-06
申请号：US11744860
申请日：2007-05-05
申请人： Yan Zhong , Abhiram Prabhakar
发明人： Yan Zhong , Abhiram Prabhakar
IPC分类号： H03M13/05
CPC分类号： H03M13/1105 , H03M13/6516
摘要： In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved.
摘要翻译：在用于解码适用于解码多等级LDPC码的低密度奇偶校验（LDPC）码的解码器中，提供了一种方法。该方法包括以下步骤：依赖于具有最大数目“1”的奇偶校验矩阵H提供用于使用存储器进行解码的存储器; 使用多个列更新单元，更新列并行并同时生成消息; 并使用多个行更新单元，并行地并行地生成消息。由此提供了逻辑和存储器中的改进的架构，使得实现了改进的吞吐量，功耗和存储器区域。

13. 发明授权

US6157684A One bit matched filter with low complexity and high speed 有权
标题翻译：一个位匹配滤波器，复杂度低，速度快
公开(公告)号：US6157684A
公开(公告)日：2000-12-05
申请号：US172973
申请日：1998-10-14
申请人： Lin Yang , Yan Zhong , Manouchehr S. Rafie
发明人： Lin Yang , Yan Zhong , Manouchehr S. Rafie
IPC分类号： G06F17/15 , H04B1/7093 , H04L27/06
CPC分类号： H04B1/7093 , G06F17/15
摘要： Described is an one bit matched filter for generating a sequences of correlations between a signal bit stream and a sample stream of n sample bits. The n sample bits are arranged in a rang of n bit positions n, n-1, . . . , 2, 1. Among the n sample bits, m boundary positions are defined based on the bit pattern of the sample stream, where m
摘要翻译：描述了一个一比特匹配滤波器，用于产生信号比特流和n个采样比特的采样流之间的相关序列。 n个采样位以n位n，n-1的排列排列。。。，2,1。在n个采样位中，m个边界位置基于样本流的位模式来定义，其中m

14. 外观设计

USD954038S1 Phone case 有权
公开(公告)号：USD954038S1
公开(公告)日：2022-06-07
申请号：US29800172
申请日：2021-07-19
申请人： Yan Zhong
设计人： Yan Zhong

15. 发明授权

US08248780B2 All-in-one computer 失效
标题翻译：一体机电脑
公开(公告)号：US08248780B2
公开(公告)日：2012-08-21
申请号：US12787826
申请日：2010-05-26
申请人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
发明人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
IPC分类号： H05K7/20 , A47B81/00 , F28F7/00
CPC分类号： G06F1/16
摘要： An all-in-one computer includes a monitor, a motherboard, a power supply, and a support mechanism supporting the monitor. The support mechanism includes a base, and a support stand fixed on the base and connected to the monitor. The support stand defines a cavity to receive the motherboard and the power supply. The motherboard and the power supply are electrically connected to the monitor.
摘要翻译：一体式电脑包括显示器，主板，电源以及支持显示器的支撑机构。支撑机构包括基座和固定在基座上并连接到监视器的支撑架。支撑架定义了一个接收母板和电源的腔体。主板和电源电连接到显示器。

16. 发明申请

US20080028282A1 RECEIVER ARCHITECTURE HAVING A LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD FOR MEMORY REDUCTION 审中-公开
标题翻译：具有用于减少存储器的改进的LLR更新方法的LDPC解码器的接收机架构
公开(公告)号：US20080028282A1
公开(公告)日：2008-01-31
申请号：US11557491
申请日：2006-11-07
申请人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
发明人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
IPC分类号： H03M13/03
CPC分类号： H03M13/116 , H03M13/1102 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/114 , H03M13/152 , H03M13/251 , H03M13/2732 , H03M13/2906 , H03M13/6505
摘要： The present invention provides a reduced memory implementation for the min-sum algorithm compared to traditional hardware implementations. The improvement includes innovative MIN_SUM method with reduced memory requirements suitable of computer implementation that combines the traditional row update process and column update process into a single process, in that the traditional CNU unit and VNU unit are combined into a single CVNU unit. The improvement not only reduces the time required for decoding by half, but also reduces the logic and routing efforts. Furthermore, instead of storing the whole intermediate LLR values using a significant number of memories, only a set of parameters associated with the intermediate LLR values is stored. The set of parameters includes: 1. sign of LLR; 2. the minimum LLR, 3. sub-minimum LLR, and 4. the column location of minimum value in each row. Therefore, as compared with the traditional LDPC decoder implementation, the required memory size of the present invention is significantly or tremendously reduced.
摘要翻译：与传统硬件实现相比，本发明提供了用于最小和算法的减少的存储器实现。该改进包括创新的MIN_SUM方法，具有较少的内存要求，适合计算机实现，将传统的行更新过程和列更新过程组合到一个过程中，传统的CNU单元和VNU单元组合成一个CVNU单元。该改进不仅将解码所需的时间缩短了一半，而且减少了逻辑和布线工作。此外，代替使用大量存储器存储整个中间LLR值，仅存储与中间LLR值相关联的一组参数。参数集包括：1. LLR的符号; 2.最小LLR，3. sub-minimum LLR和4.每行最小值的列位置。因此，与传统的LDPC解码器实现相比，本发明所需的存储器大小显着或大大降低。

17. 发明授权

US07266749B1 Trellis construction based on parity check matrix for BCH code 失效
标题翻译：基于BCH码奇偶校验矩阵的网格构建
公开(公告)号：US07266749B1
公开(公告)日：2007-09-04
申请号：US10186128
申请日：2002-06-27
申请人： Yan Zhong , Lin Yang
发明人： Yan Zhong , Lin Yang
IPC分类号： H04L1/14
CPC分类号： H03M13/152 , H03M13/3944 , H04L1/0058
摘要： A method for constructing a simplified trellis diagram for BCH-encoded information is disclosed. BCH-encoded information is received, having a corresponding parity check matrix H. The parity check matrix H is expressed as an ordered sequence of columns of matrices. A sequence of sub-code words is provided, corresponding to one or more code words, each satisfying a given condition. A matrix Hcp, having columns that are generated as a selected permutation of the columns of the matrix H through a column-permutation-for-binary-matching process, is provided, and a sequence of sub-matrices and a corresponding sequence of permuted sub-code words is provided. A trellis diagram, representing an ordered sequence of code word transitions in the received information and symmetric about a central location, is provided for each code word c, connecting n+1 stages, numbered i=0, 1, . . . , n, in an ordered sequence.
摘要翻译：公开了一种用于构建BCH编码信息的简化网格图的方法。 BCH编码信息被接收，具有对应的奇偶校验矩阵H.奇偶校验矩阵H表示为矩阵列的有序序列。提供一个子代码字序列，对应于一个或多个代码字，每个代码字都满足给定条件。提供了具有通过列置换二进制匹配处理作为矩阵H的列的选择排列生成的列的矩阵H pc，提供矩阵和相应的排列子码字序列。对于每个代码字c，提供了连接n + 1个阶段（编号为i = 0,1）的格子图，表示接收到的信息中的码字转换的有序序列并且关于中心位置对称的格状图。。。，n，有序序列。

18. 发明授权

US08477512B2 Electronic device 失效
标题翻译：电子设备
公开(公告)号：US08477512B2
公开(公告)日：2013-07-02
申请号：US12777413
申请日：2010-05-11
申请人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
发明人： Jun-Jie Zheng , Yan Zhong , Xin Ji , Wen-Hsiang Hung
IPC分类号： H05K1/11
CPC分类号： G06F1/1601
摘要： An electronic device includes a main frame structure, a plurality of functional modules fixed to the main frame structure, a plurality of cables connecting the functional modules, a cable collector board fixed to the main frame structure, and a motherboard detachably connected to the main frame structure. The cable collector board includes a plurality of first printed circuits electrically collecting the cables, and a first connector electrically collecting the first printed circuits. The motherboard includes a plurality of second printed circuits and a second connector collecting the second printed circuits. The second connector is detachably electrically connected to the first connector.
摘要翻译：一种电子设备，包括主框架结构，固定到主框架结构的多个功能模块，连接功能模块的多个电缆，固定到主框架结构的电缆集电板和可拆卸地连接到主框架的主板结构体。电缆收集器板包括多个第一印刷电路，电路中收集电缆，第一连接器电接收第一印刷电路。主板包括多个第二印刷电路和收集第二印刷电路的第二连接器。第二连接器可拆卸地电连接到第一连接器。

19. 发明授权

US08199483B2 Optical disc drive retention assembly and electronic device utilizing the same 失效
标题翻译：光盘驱动器保持组件和利用其的电子设备
公开(公告)号：US08199483B2
公开(公告)日：2012-06-12
申请号：US12787820
申请日：2010-05-26
申请人： Xin Ji , Jun-Jie Zheng , Wen-Hsiang Hung , Yan Zhong
发明人： Xin Ji , Jun-Jie Zheng , Wen-Hsiang Hung , Yan Zhong
IPC分类号： G06F1/16
CPC分类号： G06F1/181 , G06F1/1601 , G06F1/187
摘要： A retention assembly for securing a optical disc drive (ODD) to a main frame of an electronic device includes a bracket and a connector. The bracket is fixed to the ODD. One of the main frame and the bracket defines a guide groove, and the other includes a slide rail movably received in the guide groove. The connector is fixed to the main frame and adjacent to the guide groove or the slide rail. The ODD is aligned to electrically connect to the connector by the at least one guide groove or the at least one slide rail.
摘要翻译：用于将光盘驱动器（ODD）固定到电子设备的主框架的保持组件包括支架和连接器。支架固定在ODD上。主框架和支架中的一个限定了引导槽，另一个包括可移动地容纳在引导槽中的滑轨。连接器固定在主框架上并与导向槽或滑轨相邻。 ODD被对准以通过至少一个引导槽或至少一个滑轨电连接到连接器。

20. 发明申请

US20080107190A1 METHOD FOR FORMING A BIT LOG-LIKELIHOOD RATIO FROM SYMBOL LOG-LIKELIHOOD RATIO 审中-公开
标题翻译：从符号记录比例计算比特记录比例的方法
公开(公告)号：US20080107190A1
公开(公告)日：2008-05-08
申请号：US11550505
申请日：2006-10-18
申请人： Yan Zhong , Dinesh Venkatachalam
发明人： Yan Zhong , Dinesh Venkatachalam
IPC分类号： H04K1/10
CPC分类号： H04L1/0052 , H04L1/0057 , H04L25/067 , H04L27/2647 , H04L27/38 , H04L2025/03414 , H04L2025/03522
摘要： In an OFDM (Orthogonal frequency-division multiplexing) communication system, a receiver comprising an inner forward error correction device, or an inner forward error correction device is provided. Either the inner forward error correction device, or the outer forward error correction device comprises an improved method for deriving a bit log-likelihood ratio derived from a symbol log-likelihood ratio. The method includes the steps of: providing two simplified parameters; and using the two simplified parameters in addition and subtraction only to derive the bit log-likelihood ratio derived from the symbol log-likelihood ratio.
摘要翻译：在OFDM（正交频分复用）通信系统中，提供包括内部前向纠错装置或内部前向纠错装置的接收机。内部前向纠错装置或外部前向纠错装置包括用于导出从符号对数似然比导出的位对数似然比的改进方法。该方法包括以下步骤：提供两个简化参数; 并且使用两个简化参数进行加法和减法仅导出从符号对数似然比导出的比特对数似然比。

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