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11. 发明授权

US4097753A Comparator circuit for a C-2C A/D and D/A converter 失效
标题翻译： C-2C A / D和D / A转换器的比较器电路
公开(公告)号：US4097753A
公开(公告)日：1978-06-27
申请号：US673178
申请日：1976-04-02
申请人： Peter William Cook , James Thomas Parrish , Stanley Everett Schuster
发明人： Peter William Cook , James Thomas Parrish , Stanley Everett Schuster
IPC分类号： H03M1/10 , H03K5/08 , H03M1/00 , H03M1/38 , H03K5/20
CPC分类号： H03M1/1245
摘要： A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.
摘要翻译：一种用于比较C-2C A / D和D / A转换器中的两个电压电平的比较器电路，其包括锁存装置中的四个交叉耦合有源器件（FET），由此使用偏移电压来补偿比较器中的不平衡。比较器包括其栅电极连接到D / A转换器的输出的第一FET，以及其栅电极连接到模拟输入电压的第二FET。第一和第二FET各自具有连接到公共电压源的电极中的一个。第三和第四FET分别具有在第一和第二公共节点分别连接到第一和第二FET的另一个电极的一个电极。比较器的输出被提供在这样的第一和第二公共节点之一处。第一和第二节点也以交叉耦合的方式分别连接到第四和第三FET的栅电极。第三和第三FET的另一个电极连接到公共相电压源。在第一和第二FET的栅电极的输入处产生偏移电压，以将比较器设置在平衡点，从而补偿四个FET的阈值电压和载流能力的差异。此外，比较器具有相对较高的输入阻抗，增益和带宽。

12. 发明授权

US06981096B1 Mapping and logic for combining L1 and L2 directories and/or arrays 失效
标题翻译：用于组合L1和L2目录和/或阵列的映射和逻辑
公开(公告)号：US06981096B1
公开(公告)日：2005-12-27
申请号：US09165490
申请日：1998-10-02
申请人： Richard E. Matick , Stanley Everett Schuster
发明人： Richard E. Matick , Stanley Everett Schuster
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/0802
摘要： Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1 and L2 directory) into a single directory, while still allowing the individual levels to use their own organization which is best for overall performance. This integration is performed without compromising the organization at each level. With some small additions to the L2 directory, it is used simultaneously to perform both the L1 and L2 directory functions. Additionally, the same organizational structure allows the L2 array to serve both as a traditional L1 and simultaneous L2 array. In one aspect of the present invention an architecture is provided for a first and second level memory hierarchy, or cache, including a first data storage array for the first level memory hierarchy; a second data storage array for the second level memory hierarchy, a single address translation directory combining the directories for the first and second level memory hierarchy into a single directory satisfying the organization requirements of both the first and second level memory hierarchy. Also provided is a system having three level memory hierarchy comprising: a single combined directory used to serve each of three separate storage arrays. Each of the storage arrays serves a respective level of the three level memory hierarchy wherein the organization of the various levels is not compromised by the use of the single combined directory.
摘要翻译：提出了将多个目录（例如L 1和L 2目录）组合到单个目录中的体系结构，方法和系统，同时仍然允许各个级别使用自己的组织，其最适合于整体性能。这种集成是在不影响各级组织的情况下进行的。通过L 2目录的一些小的添加，它同时用于执行L 1和L 2目录功能。此外，相同的组织结构允许L 2阵列作为传统的L 1和同时的L 2阵列。在本发明的一个方面，提供了一种用于第一和第二级存储器层级或高速缓存的架构，包括用于第一级存储器层级的第一数据存储阵列; 用于第二级存储器层次的第二数据存储阵列，将第一和第二级存储器层级的目录组合成满足第一和第二级存储器层次结构的组织要求的单个目录的单个地址转换目录。还提供了具有三级存储器层级的系统，包括：用于服务三个单独的存储阵列中的每一个的单个组合目录。每个存储阵列都提供三级存储器层级的相应级别，其中各级的组织不会被使用单个组合目录所影响。

13. 发明授权

US06925549B2 Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages 失效
标题翻译：异步管道控制接口使用标签值来控制通过连续流水线阶段的传递数据
公开(公告)号：US06925549B2
公开(公告)日：2005-08-02
申请号：US09746647
申请日：2000-12-21
申请人： Peter William Cook , Andrew Douglas Davies , Stanley Everett Schuster , Daniel Lawrence Stasiak
发明人： Peter William Cook , Andrew Douglas Davies , Stanley Everett Schuster , Daniel Lawrence Stasiak
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/00 , G06F9/3871 , G06F2207/3864
摘要： An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.
摘要翻译：一种在异步流水线外部管理数据的装置和方法。寻求控制的异步流水线包括数据路径和控制路径。根据本发明的方法，数据标签值在其进入异步流水线之前被分配给数据。在将数据发送到其数据路径的同时，将数据标签值发送到控制路径，使得数据标签值与其被分配的数据并行地通过异步流水线。在异步管道中的给定阶段，将数据标签值与控制标签值进行比较，只有响应于匹配控制标签值的数据标签值才允许传递到异步管道中的下一级。

14. 发明授权

US6057188A Trench capacitor structures 失效
标题翻译：沟槽电容器结构
公开(公告)号：US6057188A
公开(公告)日：2000-05-02
申请号：US19119
申请日：1998-02-05
申请人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
发明人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
IPC分类号： H01L27/108 , H01L27/11 , H01L29/94 , H01L21/8242
CPC分类号： H01L29/945 , H01L27/10829 , H01L27/1104 , Y10S257/903
摘要： An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.
摘要翻译：可以制造用作去耦电容器或存储电容器的优化的沟槽电容器结构，而不会增加工艺复杂性。作为片上去耦沟槽电容器结构，该结构降低了对外板和内板的串联电阻，并导致可接受的RC延迟，同时保持每单位面积的高电容。作为具有埋层屏蔽的存储电容器，沟槽电容器结构对α粒子和宇宙辐射引起的故障表现出高的抗扰性。沟槽电容器结构在硅衬底中包括埋入的n阱。在衬底中形成沟槽并延伸穿过埋入的n阱。在沟槽的内表面上形成电介质膜，并且在沟槽内形成为多晶硅填充物的内板与在集成电路的外围源极/漏极触点的定义期间形成的表面n +膜连接。来自沟槽的向外扩散形式的电容器的外板提供与衬底的低电阻电接触。这些电容器中的一些可以组合在非常高效的解耦电容器的X-Y阵列中。

15. 发明授权

US5890215A Electronic computer memory system having multiple width, high speed communication buffer 失效
标题翻译：具有多个宽度，高速通信缓冲器的电子计算机存储系统
公开(公告)号：US5890215A
公开(公告)日：1999-03-30
申请号：US304634
申请日：1994-09-12
申请人： Richard E. Matick , Stanley Everett Schuster
发明人： Richard E. Matick , Stanley Everett Schuster
IPC分类号： G06F12/06 , G06F12/00 , G06F12/08 , G11C7/10 , G11C11/401 , G11C11/413
CPC分类号： G11C7/1006 , G06F12/0888 , G06F12/0897
摘要： An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.
摘要翻译：电子计算机存储器系统具有用于中央处理单元和主存储器级之间的第一和第二中间存储器级。一个或多个缓冲器阵列具有两组总线。第一组缓冲器阵列总线与第一和第二中间存储器阵列的相关联的总线通信。第二组缓冲阵列总线包含少于第一存储器阵列中的总线数量的总线数。通过提供具有两组总线的一个或多个缓冲器，可以在主存储器级与缓冲器或一个中间存储器级之间传输数据，而另一中间存储器级的数据由中央处理单元进行操作。通过为缓冲器提供等于第一和第二中间存储器阵列的总线数量的一组总线，可以实现中间存储器阵列之间的高速数据传输。

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