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11. 发明授权

US06662252B1 Group and virtual locking mechanism for inter processor synchronization 有权
标题翻译：用于处理器间同步的组和虚拟锁定机制
公开(公告)号：US06662252B1
公开(公告)日：2003-12-09
申请号：US10314748
申请日：2002-12-08
申请人： John William Marshall , Kenneth H. Potter
发明人： John William Marshall , Kenneth H. Potter
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/526 , G06F2209/522
摘要： A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.
摘要翻译：组和虚拟锁定机制（GVLM）解决存在于由多个执行线程共享的资源的系统中的两类同步;（1）多址共享资源的同步; 和（2）共享资源的同时请求。广义地说，新颖的GVLM包括与每个执行线程相关联的锁定控制器功能，以及锁定由线程执行的指令，该指令操纵锁定控制器以创建紧密集成的布置，用于向共享资源发出锁定请求。多个执行线程可以在不同的处理器中执行。或者，多个执行线程可以分别在单个处理器中执行。

12. 发明授权

US06973521B1 Lock controller supporting blocking and non-blocking requests 失效
标题翻译：锁定控制器支持阻塞和非阻塞请求
公开(公告)号：US06973521B1
公开(公告)日：2005-12-06
申请号：US09572037
申请日：2000-05-16
申请人： Atri Indiresan , Felix Yuan , Iwan Kartawira , John William Marshall , Russell Schroter
发明人： Atri Indiresan , Felix Yuan , Iwan Kartawira , John William Marshall , Russell Schroter
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/526 , G06F2209/522
摘要： A lock controller supports both blocking and non-blocking lock requests issued by processors of a processing engine when attempting to access a shared resource of an intermediate network device. The non-blocking lock controller capability provides a processor with the flexibility to obtain other shared resources if the originally requested resource is not available. The blocking capability of the lock controller guarantees that each processor will eventually obtain the requested resource. By supporting both blocking and non-blocking capabilities, the lock controller provides increased flexibility and performance to the processors of the processing engine.
摘要翻译：当尝试访问中间网络设备的共享资源时，锁定控制器支持由处理引擎的处理器发出的阻塞和非阻塞锁定请求。如果原始请求的资源不可用，非阻塞锁定控制器能力使处理器具有获得其他共享资源的灵活性。锁定控制器的阻塞能力保证每个处理器最终将获得所请求的资源。通过支持阻塞和非阻塞功能，锁定控制器为处理引擎的处理器提供更大的灵活性和性能。

13. 发明授权

US06728839B1 Attribute based memory pre-fetching technique 失效
标题翻译：基于属性的内存预取技术
公开(公告)号：US06728839B1
公开(公告)日：2004-04-27
申请号：US09181251
申请日：1998-10-28
申请人： John William Marshall
发明人： John William Marshall
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： An enhanced prefetching technique enables control of internal activities of a cache memory by a processor without relying on conventional algorithms. The cache memory is contained within a processor complex of a programmable arrayed processing engine used to efficiently process data within an intermediate network station of a computer network. The cache may further assume various functions while providing an interface to an external memory of the station via a memory controller. That is, the cache may function as a read buffer, a write buffer and/or a buffer for pending atomic commands, each of which is merged into a single memory bank that can be partitioned in any manner to enable efficient utilization.
摘要翻译：增强型预取技术使得能够通过处理器来控制高速缓冲存储器的内部活动，而不依赖常规算法。缓存存储器包含在用于有效地处理计算机网络的中间网络站内的数据的可编程阵列处理引擎的处理器复合体内。高速缓存可以进一步呈现各种功能，同时经由存储器控制器向站的外部存储器提供接口。也就是说，缓存可以用作待执行的原子命令的读缓冲器，写缓冲器和/或缓冲器，每个缓冲器和/或缓冲器被合并到可以以任何方式分区以实现有效利用的单个存储体。

14. 发明授权

US06529983B1 Group and virtual locking mechanism for inter processor synchronization 有权
标题翻译：用于处理器间同步的组和虚拟锁定机制
公开(公告)号：US06529983B1
公开(公告)日：2003-03-04
申请号：US09432464
申请日：1999-11-03
申请人： John William Marshall , Kenneth H. Potter
发明人： John William Marshall , Kenneth H. Potter
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/526 , G06F2209/522
摘要： A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.
摘要翻译：组和虚拟锁定机制（GVLM）解决了具有由多个处理器共享的资源的系统中存在的两类同步：（1）多址共享资源的同步; 和（2）共享资源的同时请求。该系统是包括处理器复杂元件阵列的可编程处理引擎，每个处理器元件具有微处理器处理器。处理器复合体优选地被排列成行和列。广义地说，新颖的GVLM包括与处理器复合体的每一列相关联的锁定控制器功能和由处理器执行的锁定指令，该指令操纵锁定控制器以创建用于向共享资源发出锁定请求的紧密集成的布置。

15. 发明授权

US3958220A Enhanced error correction 失效
标题翻译：增强错误校正
公开(公告)号：US3958220A
公开(公告)日：1976-05-18
申请号：US582516
申请日：1975-05-30
申请人： John William Marshall
发明人： John William Marshall
IPC分类号： H03M13/00 , G06F3/06 , G06F11/10 , G11B20/18 , G06F11/12
CPC分类号： G11B20/1833
摘要： Multiple symbol correction employing auxiliary pointers is enhanced by unique interaction of code structures either with ambiguous auxiliary pointers or data structures for precisely locating errors. For example, a code apparatus can correct two symbols in error only with two error location pointers; with three error location pointers, the code cannot correct the errors since error location is ambiguous. Once this has been determined, the features set forth in the present invention are employed to delimit the error burst such that the code apparatus may correct two symbols in error, even with ambiguous error location pointers. With no auxiliary pointers, methods and apparatus can create such auxiliary pointers in particular data structures and error patterns.

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