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11. 发明授权

US07849466B2 Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor 有权
标题翻译：通过对多线程处理器中的控制寄存器应用掩码来控制程序线程的执行模式
公开(公告)号：US07849466B2
公开(公告)日：2010-12-07
申请号：US11180017
申请日：2005-07-12
申请人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
发明人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
IPC分类号： G06F9/46 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3851 , G06F1/3228 , G06F1/3243 , G06F9/30181 , G06F9/30189 , G06F9/3853 , G06F9/4843 , Y02D10/152 , Y02D10/24
摘要： A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.
摘要翻译：公开了一种多线程处理器设备，并且包括被配置为执行多个可执行程序线程和模式控制寄存器的处理器。模式控制寄存器包括用于控制多个可执行程序线程中的第一个的第一执行模式的第一数据字段和用于控制多个可执行程序线程中的第二个可执行程序线程的第二执行模式的第二数据字段。在特定实施例中，第一执行模式是运行模式，第二执行模式是低功率模式。

12. 发明授权

US07590824B2 Mixed superscalar and VLIW instruction issuing and processing method and system 有权
标题翻译：混合超标量和VLIW指令发布和处理方法和系统
公开(公告)号：US07590824B2
公开(公告)日：2009-09-15
申请号：US11093375
申请日：2005-03-29
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。该系列可执行指令通过各种指令依赖关联。该方法和系统进一步标识列出多个并行可执行指令的混合指令。一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。然后，根据所述各种指令依赖性，串行执行指令被串行执行。

13. 发明授权

US07398371B2 Shared translation look-aside buffer and method 有权
标题翻译：共享翻译后备缓冲区和方法
公开(公告)号：US07398371B2
公开(公告)日：2008-07-08
申请号：US11165757
申请日：2005-06-23
申请人： Erich Plondke , William C. Anderson , Lucian Codrescu
发明人： Erich Plondke , William C. Anderson , Lucian Codrescu
IPC分类号： G06F12/00 , G06F13/24
CPC分类号： G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译：共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新启用异常和可选中断，解决原因异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。

14. 发明授权

US07249463B2 Aerodynamic fastener shield for turbomachine 有权
标题翻译：用于涡轮机的气动紧固件护罩
公开(公告)号：US07249463B2
公开(公告)日：2007-07-31
申请号：US10941213
申请日：2004-09-15
申请人： William C. Anderson , Jesse Senyo , Michael J. Epstein , Zhifeng Dong
发明人： William C. Anderson , Jesse Senyo , Michael J. Epstein , Zhifeng Dong
IPC分类号： F02C7/20 , F01D25/12
CPC分类号： F01D25/243 , F05D2250/27 , F05D2250/71 , F05D2260/231 , F05D2260/607 , F05D2260/97 , Y02T50/675
摘要： A fastener shield for use in a fluid flow path within a gas turbine engine for reducing fluid drag and heating generated by fluid flow over a plurality of circumferentially spaced fasteners. The fastener shield has a radially-extending, downstream-facing mounting flange with a plurality of circumferentially spaced bolt holes positioned to receive respective engine mounting bolts therethrough and to attach the mounting flange to elements of the turbine engine. A curved, upstream-facing fastener shield cover is positioned in spaced-apart relation to the mounting flange for at least partially covering and separating an exposed, upstream-facing portion of the bolts from the fluid flow to thereby reduce drag and consequent heating of the bolts.
摘要翻译：一种用于燃气涡轮发动机内的流体流动路径中的紧固件屏蔽件，用于减少在多个周向间隔开的紧固件上的流体流动产生的流体阻力和加热。紧固件屏蔽件具有径向延伸的，面向下游的安装凸缘，多个周向间隔开的螺栓孔定位成接收相应的发动机安装螺栓，并将安装凸缘连接到涡轮发动机的元件。弯曲的面向上游的紧固件屏蔽盖与安装凸缘间隔开地定位，用于至少部分地覆盖和分离出与流体流动的螺栓的暴露的面向上游的部分，从而减少了阻力并随之而来的加热螺栓

15. 发明授权

US06898695B2 Use of a future file for data address calculations in a pipelined processor 有权
标题翻译：在流水线处理器中使用未来文件进行数据地址计算
公开(公告)号：US06898695B2
公开(公告)日：2005-05-24
申请号：US09820514
申请日：2001-03-28
申请人： William C. Anderson , Ryo Inoue
发明人： William C. Anderson , Ryo Inoue
IPC分类号： G06F9/345 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3842 , G06F9/345 , G06F9/383 , G06F9/3863
摘要： In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.
摘要翻译：在一个实施例中，流水线处理器包括用于存储由数据地址发生器（DAG）生成的更新的数据地址值的未来文件。可以将这些更新的值提供给DAG用于随后的地址计算操作。

16. 发明授权

US06866769B2 Drive head and ECM method and tool for making same 有权
标题翻译：驱动头和ECM方法及其制作工具
公开(公告)号：US06866769B2
公开(公告)日：2005-03-15
申请号：US10288921
申请日：2002-11-06
申请人： William C. Anderson , Edward I. Stamm , Vicky S. Budinger , Terry L. Lievestro
发明人： William C. Anderson , Edward I. Stamm , Vicky S. Budinger , Terry L. Lievestro
IPC分类号： B23H3/00 , B23H3/04 , B23H9/00 , C25F3/00 , B23H3/10 , C25F7/00
CPC分类号： B23H3/04 , B23H3/00 , B23H9/00
摘要： A drive head for a bolt, fastener, coupling, nut or other driveable head made from a less malleable metal such as a powder metal nickel alloy. The drive head has an upper drive portion having at least six convex corners spaced around the outer periphery thereof, each corner terminating in an edge. The drive head also has a lower flange portion adjacent to the drive portion and having an edge extending radially outwardly to at least the edge of each corner. The drive portion and the flange portion of the drive head is formed by subjecting a blank having a generally circular head to electrochemical machining (ECM). A tool is also provided for the ECM method to form the drive portion and flange portion of the drive head.
摘要翻译：用于由不太可塑的金属如粉末金属镍合金制成的螺栓，紧固件，联接器，螺母或其他可驱动头的驱动头。驱动头具有上部驱动部分，其具有围绕其外周缘间隔开的至少六个凸角，每个拐角终止于边缘。驱动头还具有与驱动部分相邻的下凸缘部分，并具有沿径向向外延伸至至少每个拐角边缘的边缘。驱动头的驱动部分和凸缘部分通过使具有大致圆形头部的坯料经受电化学加工（ECM）而形成。还提供了用于ECM方法以形成驱动头的驱动部分和凸缘部分的工具。

17. 发明授权

US5268995A Method for executing graphics Z-compare and pixel merge instructions in a data processor 失效
标题翻译：用于在数据处理器中执行图形Z比较和像素合并指令的方法
公开(公告)号：US5268995A
公开(公告)日：1993-12-07
申请号：US616973
申请日：1990-11-21
申请人： Keith E. Diefendorff , William C. Anderson
发明人： Keith E. Diefendorff , William C. Anderson
IPC分类号： G06T15/40 , G06F15/66
CPC分类号： G06T15/405
摘要： A method for performing graphics Z-compare and pixel merge operations, for use in a Z-buffering system to remove hidden surfaces when displaying a three-dimensional image, is provided. The data processing system includes a main memory for storing data and instructions, and a graphics execution unit for executing graphics instructions. The graphics execution units are connected to an instruction sequencer, which provides instructions and data operands to the execution units, via a communications bus. In response to receiving Z-compare and pixel merge instructions, the graphics execution unit compares one or more Z-axis coordinates within a first data operand to one or more Z-axis coordinates in a corresponding bit-field position within a second data operand to determine a relative Z-axis position of each of the one or more pixels associated with the one or more Z-axis coordinates. A pixel compare result bit-vector uniquely representing the possible results of comparing each of the corresponding bit-field positions is stored in a register. Utilizing the pixel compare result vector, the graphics execution unit executes a pixel merge instruction, to selectively store the pixels in an image buffer.
摘要翻译：提供了一种用于执行图形Z比较和像素合并操作的方法，用于在Z缓冲系统中用于在显示三维图像时去除隐藏的表面。数据处理系统包括用于存储数据和指令的主存储器和用于执行图形指令的图形执行单元。图形执行单元连接到指令定序器，该指令定序器通过通信总线向执行单元提供指令和数据操作数。响应于接收Z比较和像素合并指令，图形执行单元将第一数据操作数中的一个或多个Z轴坐标与第二数据操作数中的对应位域位置中的一个或多个Z轴坐标进行比较，以确定与一个或多个Z轴坐标相关联的一个或多个像素中的每一个的相对Z轴位置。唯一表示比较每个相应位域位置的可能结果的像素比较结果位向量被存储在寄存器中。利用像素比较结果向量，图形执行单元执行像素合并指令，以选择性地将像素存储在图像缓冲器中。

18. 发明授权

US4500060A Swivel-tilt platform 失效
标题翻译：旋转倾斜平台
公开(公告)号：US4500060A
公开(公告)日：1985-02-19
申请号：US387640
申请日：1982-06-11
申请人： William C. Anderson , Bruce K. Boundy , Raoul J. P. Schoumaker
发明人： William C. Anderson , Bruce K. Boundy , Raoul J. P. Schoumaker
IPC分类号： F16M11/14 , F16M11/12 , A47B91/00
CPC分类号： F16M11/126 , F16M2200/08 , Y10S248/921
摘要： A mounting pedestal for supporting a computer terminal display device or the like is disclosed. The mounting pedestal provides for 360.degree. rotation of the support platform while permitting only limited front to rear tilting of the support platform. A base member includes an annular depression in the form of a segment of a sphere in its upper surface into which a complimentary spherical segment on the underside of the tilt platform rests to provide for 360.degree. rotation of the tilt platform with respect to the stationary base. Tilting in only a front to rear mode is controlled by a pair of laterally extending cylindrical segments on the underside of the tilt platform.
摘要翻译：公开了一种用于支撑计算机终端显示装置等的安装基座。安装座可以支撑平台360°旋转，同时只允许支撑平台的前后倾斜受限。基部构件包括在其上表面中的球形段的形式的环形凹陷，倾斜平台的下侧上的互补的球形段相对于固定基座提供倾斜平台的360度旋转。仅在前后模式的倾斜由倾斜平台的下侧上的一对横向延伸的圆柱形部分控制。

19. 发明授权

US4471574A Shutter operating system 失效
标题翻译：快门操作系统
公开(公告)号：US4471574A
公开(公告)日：1984-09-18
申请号：US359389
申请日：1982-03-18
申请人： Donald L. Strange-Boston , William C. Anderson
发明人： Donald L. Strange-Boston , William C. Anderson
IPC分类号： E05F15/04 , E05F11/04
CPC分类号： E05F15/53 , E05Y2800/00 , E05Y2900/146
摘要： A shutter operating system for a shutter hinged along a horizontal axis of an opening such as a fenestration in a wall includes cables attached to the free end of the shutter which are threaded through passages in the wall above the fenestration and to a horizontal counterweight member operating multiple cable pull points evenly through use of vertical equalizer brackets and restraint roller assemblies, assisted in operation by a hydraulic or pneumatic piston assembly, which opens and closes the shutter. The shutter operating system can also be operated manually without the assistance of the hydraulic or pneumatic piston assembly.
摘要翻译：用于沿着开口的水平轴线（例如壁上的开窗）铰接的快门的快门操作系统包括附接到闸门自由端的电缆，其穿过开窗上方的壁中的通道并且穿过开口的水平配重构件通过使用垂直均衡器支架和约束辊组件，通过液压或气动活塞组件进行操作并均匀地打开和关闭活门的多个电缆拉伸点。快门操作系统也可以在没有液压或气动活塞组件的辅助下手动操作。

20. 发明申请

US20080115145A1 METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR DEBUGGING DURING POWER TRANSITIONS 有权
标题翻译：数字信号处理器在功率转换过程中调试的方法与系统
公开(公告)号：US20080115145A1
公开(公告)日：2008-05-15
申请号：US11560323
申请日：2006-11-15
申请人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
发明人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
IPC分类号： G06F3/00
CPC分类号： G06F1/3203 , G06F11/362 , G06F11/3656
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) fox processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.
摘要翻译：在通信（例如CDMA）系统中设计和使用数字信号处理器的技术，包括（但不限于）狐狸处理传输。一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。在调试寄存器和核心处理器处理或调试过程之间传送数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

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