专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5819083A Minimal sufficient buffer space for data redistribution in a parallel database system 失效
标题翻译：在并行数据库系统中用于数据重新分配的最小足够的缓冲区空间
公开(公告)号：US5819083A
公开(公告)日：1998-10-06
申请号：US116087
申请日：1993-09-02
申请人： Wen-Tzer Thomas Chen , Shih-Gong Li
发明人： Wen-Tzer Thomas Chen , Shih-Gong Li
IPC分类号： G06F17/30 , G06F15/163 , G06F13/14
CPC分类号： G06F17/30575
摘要： A method, system and program for distributing data to a first node in a parallel database system from a plurality of existing nodes. First, a minimal sufficient number of communication buffers necessary to guarantee that a table scan operation in each of the existing nodes will execute without stopping is determined. Once calculated, the minimal sufficient number of communication buffer is allocated in the memory associated with each of the existing nodes. Thus, data from each of the plurality of existing nodes to the first node can be redistributed without interruption. Unless the redistribution process has a default set of data to be redistributed, which data from which data tables in each of the plurality of existing nodes is to be distributed to the first node must be determined. The first node may either be a new node which must be registered within the parallel database system, or an existing node within an imbalanced parallel database system which has excess capacity. The minimal sufficient number of communication buffers is determined according to the ratio of a mean queuing in a communication buffer and an average time to fill a communication buffer.
摘要翻译：一种用于从多个现有节点向并行数据库系统中的第一节点分发数据的方法，系统和程序。首先，确定必要的最小足够数量的通信缓冲器，以保证在每个现有节点中的表扫描操作不停止地执行。一旦计算，在与每个现有节点相关联的存储器中分配最小足够数量的通信缓冲器。因此，可以不间断地重新分配从多个现有节点到第一节点的数据。除非再分配过程具有要重新分配的默认数据集，否则必须确定将多个现有节点中的每一个中的数据表从哪个数据表分发到第一个节点的数据。第一节点可以是必须在并行数据库系统中注册的新节点，或者具有过剩容量的不平衡并行数据库系统内的现有节点。根据通信缓冲器中的平均排队与填充通信缓冲器的平均时间的比率来确定最小数量的通信缓冲器。

12. 发明授权

US08745362B2 Operating system aware branch predictor using a dynamically reconfigurable branch history table 有权
标题翻译：使用动态可重配置分支历史表的操作系统感知分支预测器
公开(公告)号：US08745362B2
公开(公告)日：2014-06-03
申请号：US12823288
申请日：2010-06-25
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen
IPC分类号： G06F9/00
CPC分类号： G06F9/5011 , G06F9/3848 , G06F2209/507
摘要： A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.
摘要翻译：处理器资源管理器将分支历史资源分配给第一执行模式。分支历史资源用于预测分支指令的分支方向。接下来，资源管理器记录在处理器执行第二执行模式时发生的多个分支错误预测。资源管理器又根据分支错误预测的数量将分支历史资源重新分配到第二执行模式。

13. 发明申请

US20090276191A1 Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering 有权
标题翻译：使用基本块矢量聚类和飞行矢量聚类的集成电路设计模型性能评估的方法和装置
公开(公告)号：US20090276191A1
公开(公告)日：2009-11-05
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

14. 发明申请

US20080294881A1 METHOD AND APPARATUS FOR INSTRUCTION COMPLETION STALL IDENTIFICATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：信息处理系统中指示完成标识的方法和装置
公开(公告)号：US20080294881A1
公开(公告)日：2008-11-27
申请号：US11753005
申请日：2007-05-24
申请人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
发明人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
摘要翻译：信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

15. 发明授权

US06996647B2 Token swapping for hot spot management 有权
标题翻译：令牌交换热点管理
公开(公告)号：US06996647B2
公开(公告)日：2006-02-07
申请号：US10738722
申请日：2003-12-17
申请人： Ram Raghavan , Wen-Tzer Thomas Chen
发明人： Ram Raghavan , Wen-Tzer Thomas Chen
IPC分类号： G06F13/14 , G06F13/36 , H04J3/17
CPC分类号： G06F13/37
摘要： A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan registers. The controller is configured to allocate and is configured to reallocate resources among the requestor groups to efficiently manage the computer system. The loan registers account for reallocated resources such that intended preallocation of use of shared resources is closely maintained. Hence, the computer system is able to operate efficiently while preventing any single requestor or group of requestors from monopolizing shared resources.
摘要翻译：提供了一种用于在资源管理的计算机系统中有效地管理热点的方法和装置。该系统利用控制器，一系列请求者组和一系列贷款寄存器。控制器被配置为分配并被配置为在请求者组之间重新分配资源以有效地管理计算机系统。贷款登记册用于重新分配资源，以便密切维护预期分配使用共享资源。因此，计算机系统能够有效地运行，同时防止任何单个请求者或一组请求者垄断共享资源。

16. 发明授权

US06219737B1 Read request performance of a multiple set buffer pool bus bridge 失效
标题翻译：读请求性能的多集缓冲池总线桥
公开(公告)号：US06219737B1
公开(公告)日：2001-04-17
申请号：US09210134
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A bus bridge coupled between primary and secondary busses including a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to a read request transaction from the first peripheral device while leaving transactions in the second buffer set unaffected. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate mastership of the secondary bus and the source of a subsequent transaction to be received via the secondary bus. The bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus. The invention further contemplates a computer system including processor, a bus bridge as described coupled to the processor via a primary bus, a system memory, and first and second peripheral devices coupled to the bridge via a secondary bus. The bridge is configured to push posted memory write transactions stored in the first buffer set onto the primary bus ahead of a read request from the first peripheral device without affecting transactions stored in the second buffer set. The bridge is preferably configured to arbitrate mastership of the secondary bus among the peripheral devices in response to first and second request signals received by the bridge from the first and second peripheral devices respectively.
摘要翻译：耦合在主要和次要总线之间的总线桥，包括具有第一和第二缓冲器组的缓冲池和被配置为将从第一和第二外围设备接收的事务分别引导到第一和第二缓冲器组的转向逻辑。该桥被配置为在第一个缓冲器组中发布的已发布的存储器写入事务推送到主总线上，并且响应于来自第一外围设备的读取请求事务而将第二缓冲器组中的事务保持不受影响。在一个实施例中，转向逻辑被配置为接收由桥的仲裁逻辑产生的第一和第二授权信号。第一和第二授权信号指示辅助总线的主管和通过辅助总线接收的后续事务的来源。桥接器和辅助总线适用于PCI协议。主总线可以是处理器单元的主机总线或诸如PCI总线的外围总线。本发明进一步考虑包括处理器，如通过主总线耦合到处理器的总线桥，系统存储器以及通过次级总线耦合到桥的第一和第二外围设备的计算机系统。该桥被配置为在来自第一外围设备的读取请求之前将存储在第一缓冲器组中的已发布的存储器写事务推送到主总线上，而不会影响存储在第二缓冲器集中的事务。桥接器优选地被配置为响应于桥接器从第一和第二外围设备分别接收的第一和第二请求信号来仲裁外围设备中的辅助总线的掌握。

17. 发明授权

US5838995A System and method for high frequency operation of I/O bus 失效
标题翻译： I / O总线高频运行的系统和方法
公开(公告)号：US5838995A
公开(公告)日：1998-11-17
申请号：US573682
申请日：1995-12-18
申请人： Wen-Tzer Thomas Chen , Richard Allen Kelley , Danny Marvin Neal
发明人： Wen-Tzer Thomas Chen , Richard Allen Kelley , Danny Marvin Neal
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/405
摘要： An extension to an I/O bus and bridge chip is provided which allows higher speed operations. This includes control logic which switches between different data transfer speeds. A host bridge interconnects a system bus with an I/O bus. Included in the host bridge is both a high frequency and low frequency clock. The bridge chip normally operates at the lower frequency and initiates communication with the I/O at this low frequency. If the I/O device is capable of operating at a higher frequency, then a control signal is transmitted from the I/O device to the bridge chip. In response to the receipt of this signal, control logic in the bridge chip causes the higher frequency clock in the bridge chip to be activated such that the host bridge, bus and I/O device are all then operating at the higher frequency.
摘要翻译：提供了对I / O总线和桥接芯片的扩展，允许更高速度的操作。这包括在不同数据传输速度之间切换的控制逻辑。主桥将系统总线与I / O总线互连。主桥包括高频和低频时钟。桥芯片通常以较低频率工作，并在该低频率下启动与I / O的通信。如果I / O设备能够以较高的频率工作，则控制信号从I / O设备发送到桥接芯片。响应于该信号的接收，桥芯片中的控制逻辑导致桥接芯片中的较高频率时钟被激活，使得主桥，总线和I / O设备全部以更高的频率工作。

18. 发明授权

US5781897A Method and system for performing record searches in a database within a computer peripheral storage device 失效
标题翻译：用于在计算机外围存储设备内的数据库中执行记录搜索的方法和系统
公开(公告)号：US5781897A
公开(公告)日：1998-07-14
申请号：US634511
申请日：1996-04-18
申请人： Wen-Tzer Thomas Chen , Renato John Recio
发明人： Wen-Tzer Thomas Chen , Renato John Recio
IPC分类号： G06F17/30
CPC分类号： G06F17/30477 , G06F17/30492 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： A method for record searching in a database within a computer system are disclosed. The computer system includes a main processor, a main memory, and a peripheral storage device having a secondary processor. In accordance with the method of the present invention, a command block specifying a search string for record searching in at least one database table of the database is prepared. Subsequently, the command block is issued from the main processor to the secondary processor within the peripheral storage device of the computer system. The secondary processor within the peripheral storage device is then utilized to read the database table(s) into a memory within the peripheral storage device, in response to a receipt of the command block. The search string in the command block is compared to each record of the database table(s) within the memory of the peripheral storage device to identify all the records therein which contain the search string. Finally, all identified records which contain the search string are moved from the memory of the peripheral storage device to the main memory within the computer system, such that database record searching may be performed in a more efficient manner.
摘要翻译：公开了一种在计算机系统内的数据库中进行记录搜索的方法。计算机系统包括主处理器，主存储器和具有辅助处理器的外围存储设备。根据本发明的方法，准备在数据库的至少一个数据库表中指定用于记录搜索的搜索字符串的命令块。随后，命令块从计算机系统的外围存储设备中的主处理器发送到二级处理器。响应于接收到命令块，外围存储设备中的辅助处理器然后用于将数据库表读取到外围存储设备内的存储器中。将命令块中的搜索字符串与外围存储设备的存储器中的数据库表的每个记录进行比较，以识别其中包含搜索字符串的所有记录。最后，将包含搜索字符串的所有识别的记录从外围存储设备的存储器移动到计算机系统内的主存储器，使得可以以更有效的方式执行数据库记录搜索。

19. 发明申请

US20110320793A1 OPERATING SYSTEM AWARE BRANCH PREDICTOR USING A DYNAMICALLY RECONFIGURABLE BRANCH HISTORY TABLE 有权
标题翻译：使用动态可重新分支历史表的操作系统AWARE分支预测器
公开(公告)号：US20110320793A1
公开(公告)日：2011-12-29
申请号：US12823288
申请日：2010-06-25
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen
IPC分类号： G06F9/38
CPC分类号： G06F9/5011 , G06F9/3848 , G06F2209/507
摘要： A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.
摘要翻译：处理器资源管理器将分支历史资源分配给第一执行模式。分支历史资源用于预测分支指令的分支方向。接下来，资源管理器记录在处理器执行第二执行模式时发生的多个分支错误预测。资源管理器又根据分支错误预测的数量将分支历史资源重新分配到第二执行模式。

20. 发明授权

US07069390B2 Implementation of a pseudo-LRU algorithm in a partitioned cache 失效
标题翻译：在分区高速缓存中实现伪LRU算法
公开(公告)号：US07069390B2
公开(公告)日：2006-06-27
申请号：US10655401
申请日：2003-09-04
申请人： Wen-Tzer Thomas Chen , Peichun Peter Liu , Kevin C. Stelzer
发明人： Wen-Tzer Thomas Chen , Peichun Peter Liu , Kevin C. Stelzer
IPC分类号： G06F12/12
CPC分类号： G06F12/123 , G06F12/0802 , Y10S707/99945 , Y10S707/99948
摘要： The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.
摘要翻译：本发明提供了关联高速缓存的多个分割方式。提供了一种伪最近最少使用的二叉树，也是分配二叉树的一种方式，并且信号是从分配二叉树的方式导出的，作为映射分区的函数。从分区二叉树和伪最小最近使用的二进制树的方式组合信号。高速缓存行替换信号可用于根据伪最近最少使用的二叉树和从分区二叉树方式导出的信号来选择分区的一种方式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式