专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08781110B2 Unified system architecture for elliptic-curve cryptography 有权
标题翻译：椭圆曲线加密的统一系统架构
公开(公告)号：US08781110B2
公开(公告)日：2014-07-15
申请号：US11772163
申请日：2007-06-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04L9/30 , H04L9/28 , H04L9/00 , G06F7/72 , H04K1/00
CPC分类号： H04L9/3066 , G06F7/5324 , G06F7/725
摘要： A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.
摘要翻译：提供了一种执行公钥加密的系统。该系统支持诸如Rivert，Shamir，Aldeman（RSA）和Diffie-Hellman密钥交换（DH）和椭圆曲线加密系统（ECC）的多个公共密钥加密算法的数学运算。系统支持主域和不同的复合二进制域。

12. 发明申请

US20090164546A1 METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) 有权
标题翻译：有效的可循环冗余检查（CRC）的方法和装置
公开(公告)号：US20090164546A1
公开(公告)日：2009-06-25
申请号：US11963147
申请日：2007-12-21
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/523
CPC分类号： G06F7/724 , G06F7/72 , H03M13/09
摘要： A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.
摘要翻译：一种在循环冗余校验（CRC）电路中优化多个还原级中的每一个以产生数据块的残差的方法和装置减少了用于执行减少的区域，同时通过多个阶段保持相同的延迟还原逻辑。在CRC减少电路中，Karatsuba算法，经典乘法和串行划分的混合混合结果导致平均面积减少了约20％，而关键路径延迟没有减少。

13. 发明申请

US20080240422A1 Efficient advanced encryption standard (AES) Datapath using hybrid rijndael S-Box 失效
标题翻译：高效的高级加密标准（AES）使用混合rijndael S-Box的数据路径
公开(公告)号：US20080240422A1
公开(公告)日：2008-10-02
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

14. 发明申请

US20080240421A1 Method and apparatus for advanced encryption standard (AES) block cipher 有权
标题翻译：高级加密标准（AES）块密码的方法和装置
公开(公告)号：US20080240421A1
公开(公告)日：2008-10-02
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译：可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。此外，延迟可能隐藏在非关键的最后一轮。

15. 发明授权

US08380777B2 Normal-basis to canonical-basis transformation for binary galois-fields GF(2m) 有权
标题翻译：二进制Galois-field的典型基变换法（2m）
公开(公告)号：US08380777B2
公开(公告)日：2013-02-19
申请号：US11772176
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以所有形式的所有形式的特殊不可约多项式提供了从正常形式到规范形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

16. 发明授权

US07986779B2 Efficient elliptic-curve cryptography based on primality of the order of the ECC-group 有权
标题翻译：基于ECC组的顺序的有效椭圆曲线加密
公开(公告)号：US07986779B2
公开(公告)日：2011-07-26
申请号：US11772170
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/725 , G06F5/01
摘要： Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.
摘要翻译：通过最小化移位操作的数量来减少执行用于ECC的标量点乘法的时间。通过基于ECC组的顺序的基本原理执行中间计算的点的选择性比较，通过应用模量缩放来最小化这些操作。

17. 发明申请

US20140095845A1 APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS 审中-公开
标题翻译：有效执行布尔函数的装置和方法
公开(公告)号：US20140095845A1
公开(公告)日：2014-04-03
申请号：US13631807
申请日：2012-09-28
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
IPC分类号： G06F9/30
摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
摘要翻译：描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中，布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

18. 发明授权

US08380767B2 Polynomial-basis to normal-basis transformation for binary Galois-Fields GF(2m) 有权
标题翻译：对于二值Galois-Fields GF（2m）的正态基变换的多项式
公开(公告)号：US08380767B2
公开(公告)日：2013-02-19
申请号：US11772172
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以全1形式的特殊不可约多项式，提供了从多项式基形式到正态形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

19. 发明授权

US08346839B2 Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box 失效
标题翻译：使用混合rijndael S盒的高效加密标准（AES）数据通路
公开(公告)号：US08346839B2
公开(公告)日：2013-01-01
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： G06F7/52
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

20. 发明授权

US08005210B2 Modulus scaling for elliptic-curve cryptography 有权
标题翻译：椭圆曲线加密的模量缩放
公开(公告)号：US08005210B2
公开(公告)日：2011-08-23
申请号：US11772165
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/72 , G06F5/01 , G06F7/723 , G06F7/725 , H04L9/3066
摘要： Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.
摘要翻译：使用缩减技术的模量缩放通过避免移位和乘法运算来减少执行模数运算的时间。可以将模量缩放应用于整数和二进制字段，并且基于用于模数运算的选定的缩减技术来选择缩放倍数因子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式