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11. 发明申请

US20140048882A1 TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权
标题翻译：门工功能工程技术降低平面CMOS器件中的短路通道效应
公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译：在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i）存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。

12. 发明申请

US20130260525A1 LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION 有权
标题翻译： SRAM扩展中的低延伸剂量植入
公开(公告)号：US20130260525A1
公开(公告)日：2013-10-03
申请号：US13438437
申请日：2012-04-03
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.
摘要翻译：一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

13. 发明申请

US20130256797A1 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US20130256797A1
公开(公告)日：2013-10-03
申请号：US13441048
申请日：2012-04-06
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。

14. 发明授权

US08536029B1 Nanowire FET and finFET 有权
标题翻译：纳米线FET和finFET
公开(公告)号：US08536029B1
公开(公告)日：2013-09-17
申请号：US13529334
申请日：2012-06-21
申请人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
摘要翻译：一种方法包括使有源层的第一区域变薄，以形成由有源层的第一区域和第二区域限定的有源层中的阶梯表面，在活性层上沉积限定平面的平坦化层，有源层，蚀刻以在有源层的第一区域中限定纳米线和焊盘，将纳米线悬挂在BOX层上，蚀刻有源层的第二区域中的鳍形成围绕每个纳米线的部分的第一栅极堆叠形成覆盖所述翅片的一部分的第二栅极堆叠，以及生长外延材料，其中所述外延材料限定所述纳米线FET的源极和漏极区域以及所述finFET的源极和漏极区域。

15. 发明申请

US20130176769A1 8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES 有权
标题翻译：具有肖特基二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176769A1
公开(公告)日：2013-07-11
申请号：US13345619
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C11/417 , G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
摘要翻译：一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

16. 发明授权

US08445371B2 Self-aligned contacts 有权
公开(公告)号：US08445371B2
公开(公告)日：2013-05-21
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

17. 发明授权

US08426917B2 Body-tied asymmetric P-type field effect transistor 有权
标题翻译：体系不对称P型场效应晶体管
公开(公告)号：US08426917B2
公开(公告)日：2013-04-23
申请号：US12683606
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。

18. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

19. 发明申请

US20120112310A1 DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE 有权
标题翻译：用于半导体结构的扩散面板
公开(公告)号：US20120112310A1
公开(公告)日：2012-05-10
申请号：US13351041
申请日：2012-01-16
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

20. 发明申请

US20110241120A1 Field Effect Transistor Device and Fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US20110241120A1
公开(公告)日：2011-10-06
申请号：US12754917
申请日：2010-04-06
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.
摘要翻译：一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

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