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11. 发明授权

US07528754B1 Finite impulse response digital to analog converter 有权
标题翻译：有限脉冲响应数模转换器
公开(公告)号：US07528754B1
公开(公告)日：2009-05-05
申请号：US11672810
申请日：2007-02-08
申请人： Bertan Bakkaloglu , Sayfe Kiaei , Shahin Taleie
发明人： Bertan Bakkaloglu , Sayfe Kiaei , Shahin Taleie
IPC分类号： H03M3/00
CPC分类号： H03M3/504 , H03M3/41 , H03M7/3028 , H03M7/304
摘要： A noise-shaped direct digital IF to RF DAC (DIF2RF) with embedded up-converter mixer is presented. The digital IF signal is noised shaped by a band-pass ΣΔ modulator with a single bit IF output followed by a semi-digital current-mode IF filter to attenuate out-of-band quantization noise. A current steering DAC combines scaled values of local oscillator (LO) signals as current sources for performing current steering and upconversion in a single cell.
摘要翻译：提出了一种带嵌入式上变频混频器的噪声形直接数字IF至RF DAC（DIF2RF）。数字IF信号由具有单位IF输出的带通SigmaDelta调制器形成，然后是半数字电流模式IF滤波器，以衰减带外量化噪声。电流转向DAC将本地振荡器（LO）信号的缩放值组合为用于在单个单元中执行电流转向和上变频的电流源。

12. 发明授权

US08604762B2 Low noise, low dropout regulators 有权
标题翻译：低噪声，低压差稳压器
公开(公告)号：US08604762B2
公开(公告)日：2013-12-10
申请号：US11754101
申请日：2007-05-25
申请人： Bertan Bakkaloglu , Bhaskar Aravind , Siew K. Hoon
发明人： Bertan Bakkaloglu , Bhaskar Aravind , Siew K. Hoon
IPC分类号： G05F1/10
CPC分类号： H03F3/393 , H03F1/086 , H03F1/26 , H03F2200/144 , H03F2200/168 , H03F2200/372
摘要： Low noise, low dropout regulators are described. An example low noise, low dropout regulator includes a chopping error amplifier to receive an input signal and a feedback signal and to output a modified signal having an undesired portion of the input signal shifted to a higher frequency and a regulator to receive the modified signal and to generate an output signal by filtering the undesired portion of the input signal from the modified signal.
摘要翻译：描述了低噪声，低压差稳压器。示例性低噪声，低压差调节器包括斩波误差放大器，用于接收输入信号和反馈信号，并输出具有偏移到较高频率的输入信号的不期望部分的修正信号和调节器以接收修改的信号，以及以通过从修改的信号过滤输入信号的不期望部分来产生输出信号。

13. 发明申请

US20120153917A1 LOW-TO-MEDIUM POWER SINGLE CHIP DIGITAL CONTROLLED DC-DC REGULATOR FOR POINT-OF-LOAD APPLICATIONS 有权
标题翻译：低中功率单芯片数字控制用于负载点应用的DC-DC调节器
公开(公告)号：US20120153917A1
公开(公告)日：2012-06-21
申请号：US13332343
申请日：2011-12-20
申请人： Philippe C. Adell , Bertan Bakkaloglu , Bert Vermeire , Tao Liu
发明人： Philippe C. Adell , Bertan Bakkaloglu , Bert Vermeire , Tao Liu
IPC分类号： G05F1/46
CPC分类号： H02M3/1588 , H02M2001/0009 , H02M2001/0012 , Y02B70/1466
摘要： A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.
摘要翻译：用于产生DC输出电压的DC-DC转换器包括：数字控制脉宽调制器（DPWM），用于控制开关功率级以向电感器提供变化的电压; 以及数字电压反馈电路，用于根据对应于直流输出电压的反馈电压来控制DPWM，所述数字电压反馈电路包括：第一压控振荡器，用于将反馈电压转换为第一频率信号并提供第一频率信号到第一鉴频器; 第二压控振荡器，用于将参考电压转换为第二频率信号，并将第二频率信号提供给第二频率鉴别器; 数字比较器，用于比较第一和第二鉴频器的数字输出并输出数字反馈信号; 以及用于根据数字反馈信号控制DPWM的控制器。

14. 发明授权

US08095085B2 Automatic antenna tuning unit for software-defined and cognitive radio 有权
标题翻译：用于软件定义和认知无线电的自动天线调谐单元
公开(公告)号：US08095085B2
公开(公告)日：2012-01-10
申请号：US12134438
申请日：2008-06-06
申请人： Hang Song , James T. Aberle , Bertan Bakkaloglu
发明人： Hang Song , James T. Aberle , Bertan Bakkaloglu
IPC分类号： H03C1/52 , H04K3/00
CPC分类号： H03J3/06 , H03J2200/10
摘要： A closed-loop controlled antenna tuning unit (ATU) system includes a return loss detector connected to sample an RF signal generated by a signal source to provide a return loss signal. A matching state searching circuit is connected to receive the return loss signal and, in response, selectively store a return loss value and an impedance matching state. A central controller is connected to provide a switch control signal and apply an optimum matching state to the impedance synthesizer at the conclusion of the matching state search. An impedance synthesizer is responsive to the switch control signal for coupling a radio frequency signal and matching the impedance of an antenna to a signal source.
摘要翻译：闭环控制的天线调谐单元（ATU）系统包括一个回波损耗检测器，连接到采样信号源产生的RF信号以提供回波损耗信号。连接匹配状态搜索电路以接收回波损耗信号，作为响应，选择性地存储回波损耗值和阻抗匹配状态。连接中央控制器以提供开关控制信号，并且在匹配状态搜索结束时向阻抗合成器施加最佳匹配状态。阻抗合成器响应于开关控制信号，用于耦合射频信号并将天线的阻抗与信号源匹配。

15. 发明申请

US20110063146A1 MULTISTAGE CHOPPER STABILIZED DELTA-SIGMA ADC WITH REDUCED OFFSET 有权
标题翻译：多功能切割器稳定的DELTA-SIGMA ADC具有减少偏移
公开(公告)号：US20110063146A1
公开(公告)日：2011-03-17
申请号：US12560096
申请日：2009-09-15
申请人： Wallace Edward Matthews , Bertan Bakkaloglu , Brian Phillip Lum-Shue-Chan
发明人： Wallace Edward Matthews , Bertan Bakkaloglu , Brian Phillip Lum-Shue-Chan
IPC分类号： H03M3/00 , H03M1/06
CPC分类号： H03M3/34 , H03M3/43 , H03M3/456
摘要： A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.
摘要翻译：相对较低的频率斩波操作被应用于Δ-ΣADC以减少由非理想分量操作引起的DC偏移。顺序斩波发生在闭环之外，并且可能包括斩波周期的一部分的反相极性反馈。嵌套斩波涉及在闭环内进行斩波，并且可以包括反相极性反馈和时移。顺序和嵌套斩波的反馈补偿允许在所需时间结合采样和量化事件提供正确的极性反馈。在嵌套斩波期间，积分电容器可以相对极性交换，以保留所需极性的残留转换信息。 ADC操作与温度无关，避免了对有用信号的修改，导致更高的精度。

16. 发明申请

US20080001585A1 LOW NOISE, LOW DROPOUT REGULATORS 有权
标题翻译：低噪声，低压差调节器
公开(公告)号：US20080001585A1
公开(公告)日：2008-01-03
申请号：US11754101
申请日：2007-05-25
申请人： Bertan Bakkaloglu , Bhaskar Aravind , Siew Hoon
发明人： Bertan Bakkaloglu , Bhaskar Aravind , Siew Hoon
IPC分类号： G05F1/10
CPC分类号： H03F3/393 , H03F1/086 , H03F1/26 , H03F2200/144 , H03F2200/168 , H03F2200/372
摘要： Low noise, low dropout regulators are described. An example low noise, low dropout regulator includes a chopping error amplifier to receive an input signal and a feedback signal and to output a modified signal having an undesired portion of the input signal shifted to a higher frequency and a regulator to receive the modified signal and to generate an output signal by filtering the undesired portion of the input signal from the modified signal.
摘要翻译：描述了低噪声，低压差稳压器。示例性低噪声，低压差调节器包括斩波误差放大器，用于接收输入信号和反馈信号，并输出具有偏移到较高频率的输入信号的不期望部分的修正信号和调节器以接收修改的信号，以及以通过从修改的信号过滤输入信号的不期望部分来产生输出信号。

17. 发明申请

US20050225465A1 Current-steering digital-to-analog converter having a minimum charge injection latch 有权
标题翻译：具有最小电荷注入锁存器的电流转向数模转换器
公开(公告)号：US20050225465A1
公开(公告)日：2005-10-13
申请号：US10823046
申请日：2004-04-13
申请人： Weibiao Zhang , Bertan Bakkaloglu
发明人： Weibiao Zhang , Bertan Bakkaloglu
IPC分类号： H03M1/06 , H03M1/66 , H03M1/74
CPC分类号： H03M1/0624 , H03M1/747
摘要： A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion. Furthermore, the distortion as a result of the clock signal fed through each transistor in the first and second subcircuit portions cancel each other.
摘要翻译：用于驱动电流转向数模转换器（DAC）的单元电流单元的锁存架构，其减小输出电流源晶体管的漏源电压变化，并减少输入数字信号的不期望的注入的耦合因为这里呈现时钟信号。此外，该锁存器有助于在代码转换期间实现较低的毛刺，并提高动态性能。锁存器有效地使用锁存器架构内大多数晶体管的固有RC延迟，以实现互补控制信号的最佳交叉点。通过引入在代码转换期间关闭而不损害DAC更新速度的晶体管（904,906,932和934）来减少不需要的输入注入或串扰。为了减少谐波失真，避免了当前持有的和新的输入之间的冲突。此外，作为通过第一和第二子电路中的每个晶体管馈送的时钟信号的结果的失真彼此抵消。

18. 发明申请

US20120101595A1 COMMUNICATION INTERFACE FOR SENSORY STIMULATION 有权
标题翻译：用于感觉刺激的通信接口
公开(公告)号：US20120101595A1
公开(公告)日：2012-04-26
申请号：US13264777
申请日：2010-04-21
申请人： Ranu Jung , Kenneth Horch , James J. Abbas , Stephen Phillips , Bertan Bakkaloglu , Seung-Jae Kim
发明人： Ranu Jung , Kenneth Horch , James J. Abbas , Stephen Phillips , Bertan Bakkaloglu , Seung-Jae Kim
IPC分类号： A61F2/72
CPC分类号： A61F2/68 , A61F2002/6827 , A61F2002/7615 , A61F2002/7625 , A61N1/36014
摘要： Techniques, apparatuses, and systems for interfacing multiple sensors with a biological system can include amplifying signals from respective sensors associated with an external device; modulating the amplified signals based on respective different frequency values; and summing the modulated signals to produce an output signal to stimulate a biological system.
摘要翻译：用于将多个传感器与生物系统接口的技术，装置和系统可以包括放大与外部设备相关联的各个传感器的信号; 基于相应的不同频率值调制放大的信号; 并将调制信号相加以产生输出信号以刺激生物系统。

19. 发明授权

US07999710B2 Multistage chopper stabilized delta-sigma ADC with reduced offset 有权
标题翻译：多级斩波器稳定的Δ-ΣADC具有减小的偏移
公开(公告)号：US07999710B2
公开(公告)日：2011-08-16
申请号：US12560096
申请日：2009-09-15
申请人： Wallace Edward Matthews , Bertan Bakkaloglu , Brian Phillip Lum-Shue-Chan
发明人： Wallace Edward Matthews , Bertan Bakkaloglu , Brian Phillip Lum-Shue-Chan
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/43 , H03M3/456
摘要： A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.
摘要翻译：相对较低的频率斩波操作被应用于Δ-ΣADC以减少由非理想分量操作引起的DC偏移。顺序斩波发生在闭环之外，并且可能包括斩波周期的一部分的反相极性反馈。嵌套斩波涉及在闭环内进行斩波，并且可以包括反相极性反馈和时移。顺序和嵌套斩波的反馈补偿允许在所需时间结合采样和量化事件提供正确的极性反馈。在嵌套斩波期间，积分电容器可以相对极性交换，以保留所需极性的残留转换信息。 ADC操作与温度无关，避免了对有用信号的修改，导致更高的精度。

20. 发明申请

US20090046030A1 Automatic Antenna Tuning Unit for Software-Defined and Cognitive Radio 有权
标题翻译：用于软件定义和认知无线电的自动天线调谐单元
公开(公告)号：US20090046030A1
公开(公告)日：2009-02-19
申请号：US12134438
申请日：2008-06-06
申请人： Hang Song , James T. Aberle , Bertan Bakkaloglu
发明人： Hang Song , James T. Aberle , Bertan Bakkaloglu
IPC分类号： H03H7/40 , H01Q1/50
CPC分类号： H03J3/06 , H03J2200/10
摘要： A closed-loop controlled antenna tuning unit (ATU) system includes a return loss detector connected to sample an RF signal generated by a signal source to provide a return loss signal. A matching state searching circuit is connected to receive the return loss signal and, in response, selectively store a return loss value and an impedance matching state. A central controller is connected to provide a switch control signal and apply an optimum matching state to the impedance synthesizer at the conclusion of the matching state search. An impedance synthesizer is responsive to the switch control signal for coupling a radio frequency signal and matching the impedance of an antenna to a signal source.
摘要翻译：闭环控制的天线调谐单元（ATU）系统包括一个回波损耗检测器，连接到采样信号源产生的RF信号以提供回波损耗信号。连接匹配状态搜索电路以接收回波损耗信号，作为响应，选择性地存储回波损耗值和阻抗匹配状态。连接中央控制器以提供开关控制信号，并且在匹配状态搜索结束时向阻抗合成器施加最佳匹配状态。阻抗合成器响应于开关控制信号，用于耦合射频信号并将天线的阻抗与信号源匹配。

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