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11. 发明授权

US08125006B2 Array of low resistive vertical diodes and method of production 失效
标题翻译：低电阻垂直二极管阵列及其制作方法
公开(公告)号：US08125006B2
公开(公告)日：2012-02-28
申请号：US12188401
申请日：2008-08-08
申请人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： H01L29/768
CPC分类号： H01L27/24 , Y10S257/91
摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
摘要翻译：描述了包括存储器单元阵列和相应的制造方法的集成电路。每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

12. 发明授权

US07642572B2 Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US07642572B2
公开(公告)日：2010-01-05
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

13. 发明申请

US20090261312A1 INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD 审中-公开
标题翻译：集成电路，包括低电阻垂直二极管阵列和方法
公开(公告)号：US20090261312A1
公开(公告)日：2009-10-22
申请号：US12105867
申请日：2008-04-18
申请人： Ulrike Gruening-von Schwerin
发明人： Ulrike Gruening-von Schwerin
IPC分类号： H01L47/00 , H01L21/82 , H01L21/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined portion and protrusions. The diode includes an active area located between two adjacent protrusions.
摘要翻译：一种集成电路，包括一个低电阻垂直二极管阵列和方法。一个实施例提供了至少部分地形成在衬底中用于选择多个存储器单元之一的二极管阵列。二极管耦合到字线。字线包括直线部分和突起。二极管包括位于两个相邻突起之间的有源区。

14. 发明申请

US20090236658A1 ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION 审中-公开
标题翻译：垂直的TRIGATE晶体管阵列和生产方法
公开(公告)号：US20090236658A1
公开(公告)日：2009-09-24
申请号：US12050230
申请日：2008-03-18
申请人： Ulrike Gruening-von Schwerin
发明人： Ulrike Gruening-von Schwerin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/26586 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L29/4236 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor.
摘要翻译：公开了垂直三角晶体管阵列和生产方法。一个实施例提供了用于选择多个存储单元之一的选择晶体管阵列。选择晶体管是垂直三极管晶体管。

15. 发明授权

US07362608B2 Phase change memory fabricated using self-aligned processing 有权
标题翻译：使用自对准处理制造的相变存储器
公开(公告)号：US07362608B2
公开(公告)日：2008-04-22
申请号：US11366151
申请日：2006-03-02
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory includes phase change elements between the second conductive lines and contacting the first conductive lines and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.
摘要翻译：存储器包括行和列中提供阵列的晶体管，跨阵列的列中的第一导电线以及跨越阵列的行中的介电材料封装的第二导电线。每个第二导线与每行中的晶体管的源极 - 漏极路径的一侧耦合。存储器包括第二导线之间的相变元件，并与第一导线接触并与第一导线自对准。每个相变元件耦合到晶体管的源 - 漏路径的另一侧。

16. 发明申请

US20070287251A1 Method for forming a memory device with at least one memory cell, in particular a phase change memory cell, and memory device 审中-公开
标题翻译：用于形成具有至少一个存储单元，特别是相变存储单元的存储器件和存储器件的方法
公开(公告)号：US20070287251A1
公开(公告)日：2007-12-13
申请号：US11449050
申请日：2006-06-08
申请人： Ulrike Gruening-von Schwerin
发明人： Ulrike Gruening-von Schwerin
IPC分类号： H01L21/336
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/1675
摘要： A method for forming a memory device with at least one memory cell, the memory cell including a volume of switching active material is disclosed. The method includes the process of depositing a first layer of insulating material on a substrate, depositing a layer of switching active material on the layer of insulating material, patterning the layer of switching active material to form volumes of switching active material. A second layer of insulating material is deposited. Vias are formed in the layers of the first insulating material, the switching active material and the second layer of insulating material in one method process. The vias are filled with a conductive material to form first and second electrode contacts for electrically coupling the volumes of switching active material. Furthermore the invention relates to a memory device produced by using this method.
摘要翻译：公开了一种用于形成具有至少一个存储单元的存储器件的方法，所述存储器单元包括一定量的开关活性材料。该方法包括在衬底上沉积第一绝缘材料层的过程，在绝缘材料层上沉积切换活性材料层，使开关活性材料层形成图案以形成体积的开关活性材料。沉积第二层绝缘材料。在一个方法工艺中，在第一绝缘材料，开关活性材料和第二绝缘材料层的层中形成通孔。通孔填充有导电材料以形成用于电耦合开关活性材料体积的第一和第二电极触点。此外，本发明涉及使用该方法制造的存储器件。

17. 发明授权

US07875492B2 Integrated circuit including a memory fabricated using self-aligned processing 有权
标题翻译：集成电路包括使用自对准处理制造的存储器
公开(公告)号：US07875492B2
公开(公告)日：2011-01-25
申请号：US12020988
申请日：2008-01-28
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
摘要翻译：集成电路包括提供阵列的行和列的晶体管，跨阵列的列中的导电线以及与导电线接触并与导电线自对准的电阻率变化材料元件。集成电路包括与电阻率变化材料元件接触的电极，每个电极与导电线自对准并且耦合到晶体管的源极 - 漏极路径的一侧。

18. 发明授权

US07727837B2 Method of producing an integrated circuit having a capacitor with a supporting layer 失效
标题翻译：一种具有带支撑层的电容器的集成电路的制造方法
公开(公告)号：US07727837B2
公开(公告)日：2010-06-01
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

19. 发明申请

US20100032635A1 ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION 失效
标题翻译：低电阻垂直二极管阵列及其生产方法
公开(公告)号：US20100032635A1
公开(公告)日：2010-02-11
申请号：US12188401
申请日：2008-08-08
申请人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： H01L47/00 , H01L29/66 , H01L21/00
CPC分类号： H01L27/24 , Y10S257/91
摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
摘要翻译：描述了包括存储器单元阵列和相应的制造方法的集成电路。每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

20. 发明授权

US07495946B2 Phase change memory fabricated using self-aligned processing 失效
标题翻译：使用自对准处理制造的相变存储器
公开(公告)号：US07495946B2
公开(公告)日：2009-02-24
申请号：US11366706
申请日：2006-03-02
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.
摘要翻译：存储器包括行和列中的晶体管，其在阵列中的列中提供阵列和导线。存储器包括与导线接触并与导线自对准的相变元件。每个相变元件耦合到晶体管的源 - 漏路径的一侧。

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