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11. 发明授权

US06391756B1 Semiconductor processing methods of forming contact openings 有权
标题翻译：形成接触开口的半导体加工方法
公开(公告)号：US06391756B1
公开(公告)日：2002-05-21
申请号：US09387040
申请日：1999-08-31
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被移除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

12. 发明授权

US06764934B2 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random 失效
标题翻译：形成接触开口的半导体加工方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（电容）电路的方法
公开(公告)号：US06764934B2
公开(公告)日：2004-07-20
申请号：US10137100
申请日：2002-05-01
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H04L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

13. 发明授权

US06790663B2 Methods of contacting lines and methods of forming an electrical contact in a semiconductor device 有权
标题翻译：接触线的方法和在半导体器件中形成电接触的方法
公开(公告)号：US06790663B2
公开(公告)日：2004-09-14
申请号：US10098659
申请日：2002-03-12
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L214763
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

14. 发明授权

US06753243B2 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY 有权
标题翻译：形成接触开口的半导体处理方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（DRAM）电路的方法
公开(公告)号：US06753243B2
公开(公告)日：2004-06-22
申请号：US10280452
申请日：2002-10-25
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

15. 发明授权

US06423620B1 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY 有权
公开(公告)号：US06423620B1
公开(公告)日：2002-07-23
申请号：US09935474
申请日：2001-08-21
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

16. 发明授权

US06406954B1 Method for forming out-diffusing a dopant from the doped polysilicon into the N-type and P-type doped portion 失效
标题翻译：用于将掺杂剂从掺杂多晶硅扩散到N型和P型掺杂部分中的方法
公开(公告)号：US06406954B1
公开(公告)日：2002-06-18
申请号：US09388559
申请日：1999-09-02
申请人： Shubneesh Batra , Luan C. Tran , Tyler A. Lowrey
发明人： Shubneesh Batra , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped portion. A second opening is formed to extend through the mask material and to the p-type doped portion. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions. In another aspect, the invention includes methods of forming CMOS constructions. In yet another aspect, the invention encompasses methods of forming DRAM constructions.
摘要翻译：一方面，本发明包括将掺杂剂扩散到半导体衬底的n型和p型掺杂区域中的半导体处理方法。提供半导体材料。半导体材料具有第一部分和第二部分。第一部分是p型掺杂部分，第二部分是n型掺杂部分。在p型和n型掺杂部分上形成掩模材料。形成第一开口以延伸穿过掩模材料和n型掺杂部分。形成第二开口以延伸穿过掩模材料和p型掺杂部分。导电掺杂多晶硅形成在第一和第二开口内。掺杂剂从导电掺杂多晶硅扩散到n型和p型掺杂部分。另一方面，本发明包括形成CMOS结构的方法。在另一方面，本发明包括形成DRAM结构的方法。

17. 发明授权

US06356500B1 Reduced power DRAM device and method 有权
标题翻译：降低功耗的DRAM器件和方法
公开(公告)号：US06356500B1
公开(公告)日：2002-03-12
申请号：US09643945
申请日：2000-08-23
申请人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
发明人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C5/14 , G11C11/4074
摘要： A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
摘要翻译：公开了一种采用降低功耗的方案的存储器件和方法。通过将存储器阵列扇区划分成存储器子阵列，存储器件可以为需要上电的存储器子阵列或替代地断电提供电力。这降低了与高速和高容量存储器件相关联的功耗和发热。

18. 发明授权

US06456535B2 Dynamic flash memory cells with ultra thin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06456535B2
公开(公告)日：2002-09-24
申请号：US09882920
申请日：2001-06-15
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

19. 发明授权

US06249460B1 Dynamic flash memory cells with ultrathin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06249460B1
公开(公告)日：2001-06-19
申请号：US09513938
申请日：2000-02-28
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

20. 发明授权

US6159790A Method of controlling outdiffusion in doped three-dimensional film by using angled implants 有权
标题翻译：通过使用倾斜植入物控制掺杂三维膜中的扩散扩散的方法
公开(公告)号：US6159790A
公开(公告)日：2000-12-12
申请号：US310489
申请日：1999-05-12
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

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