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11. 发明申请

US20130141170A1 AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING 有权
标题翻译：用于电感峰值的放大器电感共享
公开(公告)号：US20130141170A1
公开(公告)日：2013-06-06
申请号：US13312228
申请日：2011-12-06
申请人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
发明人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
IPC分类号： H03F3/68
CPC分类号： H03F3/68 , H03F1/42 , H03F3/191 , H03F3/195 , H03F3/45183 , H03F2200/36 , H03F2200/405 , H03F2203/45638 , H03F2203/45702
摘要： A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.
摘要翻译：共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

12. 发明申请

US20120223752A1 PHASE LOCKED LOOP WITH CHARGE PUMP 有权
标题翻译：充电泵的相位锁定环
公开(公告)号：US20120223752A1
公开(公告)日：2012-09-06
申请号：US13039095
申请日：2011-03-02
申请人： Ming-Chieh HUANG , Chih-Chang LIN , Tao Wen CHUNG , Chan-Hong CHERN
发明人： Ming-Chieh HUANG , Chih-Chang LIN , Tao Wen CHUNG , Chan-Hong CHERN
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L7/089 , H03L7/0893
摘要： A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.
摘要翻译：锁相环（PLL）包括配置成提供输出信号的压控振荡器（VCO）。相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。第二电荷泵被配置为接收第一控制信号并提供第二电压信号。比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。

13. 发明申请

US20130121396A1 DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS 有权
标题翻译：具有可编程功能的决策反馈均衡器
公开(公告)号：US20130121396A1
公开(公告)日：2013-05-16
申请号：US13293513
申请日：2011-11-10
申请人： Ming-Chieh HUANG , Jing Jing CHEN , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Yuwen SWEI
发明人： Ming-Chieh HUANG , Jing Jing CHEN , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Yuwen SWEI
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03687
摘要： A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.
摘要翻译：具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。延迟元素与夏天相结合。延迟元件串联连接。每个延迟元件向延迟元件提供输入信号的相应延迟信号。重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号通过通道传输的脉冲信号。

14. 发明申请

US20130082754A1 PHASE LOCKED LOOP CALIBRATION 有权
标题翻译：相位锁定校准
公开(公告)号：US20130082754A1
公开(公告)日：2013-04-04
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
发明人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
IPC分类号： H03L7/08
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

15. 发明申请

US20120032731A1 CHARGE PUMP DOUBLER 有权
标题翻译：充气泵双打
公开(公告)号：US20120032731A1
公开(公告)日：2012-02-09
申请号：US12849503
申请日：2010-08-03
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Chih-Chang LIN , Tien-Chun YANG , Yuwen SWEI
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Chih-Chang LIN , Tien-Chun YANG , Yuwen SWEI
IPC分类号： G05F3/02 , H01L25/00
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译：集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

16. 发明申请

US20120013374A1 PHASE-LOCK ASSISTANT CIRCUITRY 有权
标题翻译：相位锁定辅助电路
公开(公告)号：US20120013374A1
公开(公告)日：2012-01-19
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang LIN , Chan-Hong CHERN , Steven SWEI , Ming-Chieh HUANG , Tien-Chun YANG
发明人： Chih-Chang LIN , Chan-Hong CHERN , Steven SWEI , Ming-Chieh HUANG , Tien-Chun YANG
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

17. 发明申请

US20130127433A1 METHOD OF OPERATING VOLTAGE REGULATOR 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US20130127433A1
公开(公告)日：2013-05-23
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

18. 发明申请

US20120019302A1 LOW MINIMUM POWER SUPPLY VOLTAGE LEVEL SHIFTER 有权
标题翻译：低最低电源电压水平变换器
公开(公告)号：US20120019302A1
公开(公告)日：2012-01-26
申请号：US12843479
申请日：2010-07-26
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Chih-Chang LIN
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Chih-Chang LIN
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译：电平移位器包括一个PMOS和两个NMOS晶体管。第一NMOS晶体管的源极耦合到低电源电压。输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。输出信号耦合在PMOS和第一NMOS晶体管之间。第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1，输入信号为逻辑0。

19. 发明申请

US20140266114A1 METHOD OF OPERATING VOLTAGE REGULATOR 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US20140266114A1
公开(公告)日：2014-09-18
申请号：US14291426
申请日：2014-05-30
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
摘要翻译：电压调节器电路包括具有反相输入和非反相输入的放大器。放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。驱动器耦合在第一功率节点和输出节点之间。具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

20. 发明申请

US20120200323A1 PHASE-LOCK ASSISTANT CIRCUITRY 有权
标题翻译：相位锁定辅助电路
公开(公告)号：US20120200323A1
公开(公告)日：2012-08-09
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang LIN , Chan-Hong CHERN , Steven SWEI , Ming-Chieh HUANG , Tien-Chun YANG
发明人： Chih-Chang LIN , Chan-Hong CHERN , Steven SWEI , Ming-Chieh HUANG , Tien-Chun YANG
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

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