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11. 发明授权

US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down 有权
标题翻译： L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
公开(公告)号：US08171326B2
公开(公告)日：2012-05-01
申请号：US12785842
申请日：2010-05-24
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

12. 发明授权

US08117404B2 Misalignment predictor 有权
标题翻译：对准预测器
公开(公告)号：US08117404B2
公开(公告)日：2012-02-14
申请号：US11200771
申请日：2005-08-10
申请人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
发明人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/30145 , G06F9/3832 , G06F9/3861
摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
摘要翻译：在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。电路被配置为预测存储器操作是否不对准。由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。

13. 发明申请

US20080086622A1 Replay reduction for power saving 有权
标题翻译：节电减重
公开(公告)号：US20080086622A1
公开(公告)日：2008-04-10
申请号：US11546223
申请日：2006-10-10
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译：在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。

14. 发明申请

US20080086594A1 Uncacheable load merging 审中-公开
标题翻译：不可加载的负载合并
公开(公告)号：US20080086594A1
公开(公告)日：2008-04-10
申请号：US11545825
申请日：2006-10-10
申请人： Po-Yung Chang , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3826 , G06F12/0888 , Y02D10/13
摘要： In one embodiment, a processor comprises a buffer and a control unit coupled to the buffer. The buffer is configured to store requests to be transmitted on an interconnect on which the processor is configured to communicate. The buffer is coupled to receive a first uncacheable load request having a first address. The control unit is configured to merge the first uncacheable load request with a second uncacheable load request that is stored in the buffer responsive to a second address of the second load request matching the first address within a granularity. A single transaction on the interconnect is used for both the first and second uncacheable load requests, if merged. Separate transactions on the interconnect are used for each of the first and second uncacheable load requests if not merged.
摘要翻译：在一个实施例中，处理器包括耦合到缓冲器的缓冲器和控制单元。缓冲器被配置为存储要在处理器配置为进行通信的互连上发送的请求。缓冲器被耦合以接收具有第一地址的第一不可缓存的加载请求。所述控制单元被配置为将所述第一不可缓存的加载请求与存储在所述缓冲器中的第二不可缓存的加载请求进行合并，所述第二不可缓存的加载请求响应于在粒度内与所述第一地址匹配的第二加载请求的第二地址。如果合并，互连上的单个事务将用于第一个和第二个不可缓存的加载请求。对于第一和第二不可缓存的加载请求中的每一个，如果不合并，则互连上的单独事务将被使用。

15. 发明授权

US07203817B2 Power consumption reduction in a pipeline by stalling instruction issue on a load miss 失效
标题翻译：通过停止负载错误的指令问题，在管道中降低功耗
公开(公告)号：US07203817B2
公开(公告)日：2007-04-10
申请号：US10067038
申请日：2002-02-04
申请人： Tse-Yu Yeh
发明人： Tse-Yu Yeh
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30065 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3863 , G06F9/3867
摘要： A processor is contemplated which includes a queue configured to store one or more instructions and a control circuit coupled to the queue. The control circuit is configured to detect a replay of a first instruction due to a dependency on a load miss. In response to detecting the replay, the control circuit is configured to inhibit issuance of the one or more instructions in the queue to one or more pipelines of the processor. A carrier medium comprising one or more data structures representing the processor are also contemplated, as are a method of detecting the replay and inhibiting issuance of instructions in the queue in response to detecting the replay.
摘要翻译：可以构想一种处理器，其包括配置成存储一个或多个指令的队列和耦合到队列的控制电路。控制电路被配置为由于对负载缺失的依赖性来检测第一指令的重放。响应于检测重放，控制电路被配置为禁止将队列中的一个或多个指令发出到处理器的一个或多个管道。还考虑了包括表示处理器的一个或多个数据结构的载体介质，以及响应于检测重放来检测队列中重放和禁止发出指令的方法。

16. 发明授权

US07162613B2 Mechanism for processing speculative LL and SC instructions in a pipelined processor 失效
标题翻译：在流水线处理器中处理推测性LL和SC指令的机制
公开(公告)号：US07162613B2
公开(公告)日：2007-01-09
申请号：US11046454
申请日：2005-01-28
申请人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
发明人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.
摘要翻译：一种处理器包括第一电路和第二电路。第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。第二电路被耦合以接收第一指示。响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。也考虑了一种方法。

17. 发明授权

US07100064B2 Limiting performance in an integrated circuit to meet export restrictions 有权
公开(公告)号：US07100064B2
公开(公告)日：2006-08-29
申请号：US10158468
申请日：2002-05-30
申请人： Robert Rogenmoser , Michael C. Kim , Tse-Yu Yeh
发明人： Robert Rogenmoser , Michael C. Kim , Tse-Yu Yeh
IPC分类号： G06F1/30 , G06F1/32 , G06F1/06 , G06F1/08
CPC分类号： G06F9/3869 , G06F9/30189 , G06F9/3836
摘要： An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit. The processor responds to a blown state of the fuse by executing, during use, fewer instructions per period of time than the processor would otherwise execute.

18. 发明授权

US06430674B1 Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time 有权
标题翻译：处理器执行多个指令集（ISA），同时具有在不同流水线阶段具有多个ISA的能力
公开(公告)号：US06430674B1
公开(公告)日：2002-08-06
申请号：US09223441
申请日：1998-12-30
申请人： Jignesh Trivedi , Tse-Yu Yeh
发明人： Jignesh Trivedi , Tse-Yu Yeh
IPC分类号： G06F9455
CPC分类号： G06F9/3802 , G06F9/30076 , G06F9/30174 , G06F9/30189 , G06F9/3836 , G06F9/3857
摘要： A method and apparatus for transitioning a processor from a first mode of operation for processing a first instruction set architecture (instruction set) to a second mode of operation for processing a second set instruction set. The method provides that instructions of a first instruction set architecture (instruction set) are processed in a pipelined processor in a first mode of operation, and instructions of a second, different, instruction set, are processed in the pipelined processor in a second, different, mode of operation. While operating in one mode and before a switch to the other mode occurs, the pipeline is loaded with a set of instructions that transition the processor from one mode to the other, wherein the set of instructions are substantially insensitive to the mode that the processor operates in. The processor begins processing the set of instructions while in one mode, and finishes processing the instructions after switching to the other mode, and the set of instructions are held in a permanent memory, and are ready to be executed and do not require decoding. The processor switches mode in response to a mode switch instruction in the pipeline, and the set of instructions follow the mode switch instruction in the pipeline by a spacing which is less than the number of stages in the pipeline. The transition instructions include mode sensitive instructions that follow the mode insensitive instructions, and the mode sensitive instructions enter the pipeline after the mode switch has occurred. Further, the pipeline has alternate front end stages, one operating to decode instructions in one mode of operation, and the other to decode instructions in the other mode of operation. In addition, one of the front end stages translates instructions from one instruction set to another.
摘要翻译：一种用于将处理器从用于处理第一指令集架构（指令集）的第一操作模式转换到用于处理第二集合指令集的第二操作模式的处理器的方法和装置。该方法提供了在第一操作模式中在流水线处理器中处理第一指令集架构（指令集）的指令，并且在流水线处理器中处理第二指令集指令的第二不同的指令集，操作模式。当在一种模式下操作并且在切换到另一模式之前，流水线装载有一组将处理器从一种模式转移到另一种模式的指令，其中该组指令对处理器操作的模式基本不敏感处理器在一种模式下开始处理指令集，并且在切换到另一种模式之后完成处理指令，并且该组指令被保持在永久存储器中，并且准备好被执行并且不需要解码。处理器响应于流水线中的模式切换指令而切换模式，并且指令集在流水线中遵循小于流水线级数的间隔的模式切换指令。转换指令包括遵循模式不敏感指令的模式敏感指令，模式敏感指令在模式切换发生后进入流水线。此外，管线具有交替的前端级，一个操作用于在一种操作模式下对指令进行解码，另一个在另一种操作模式下解码指令。另外，前端级之一将指令从一个指令集转换到另一个指令集。

19. 发明授权

US5815700A Branch prediction table having pointers identifying other branches within common instruction cache lines 失效
标题翻译：分支预测表具有标识公共指令高速缓存行内的其他分支的指针
公开(公告)号：US5815700A
公开(公告)日：1998-09-29
申请号：US576954
申请日：1995-12-22
申请人： Mircea Poplingher , Tse-Yu Yeh , Wenliang Chen
发明人： Mircea Poplingher , Tse-Yu Yeh , Wenliang Chen
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3844
摘要： A branch prediction system is described for use within a microprocessor having an instruction cache capable of storing two or more instructions per cache line. Each entry of a branch prediction table (BPT) includes a value identifying whether at least one other instruction within a common cache line contains a branch. The value is referred to herein as a multiple-B bit value. The multiple-B bit value is examined by branch prediction logic while one branch prediction is being performed to determine whether a second branch prediction can be initiated for another branch within the same cache line. In one implementation, the multiple-B bit of one BPT entry is examined following a hit. A branch prediction for the entry generating a hit is initiated. Simultaneously, the BPT is reaccessed to search for an entry corresponding to another instruction within the same cache line if the multiple-B bit for the first entry was set. If the second entry is found, a secondary branch prediction is initiated. Eventually, the first branch prediction is output. If the first branch prediction is Not Taken, then the second branch prediction is output during the next clock cycle. If the first branch prediction is Taken, then the second branch prediction may be aborted as it is not needed. Method and apparatus embodiments of the invention are described.
摘要翻译：描述了一种在具有每个高速缓存行存储两个或多个指令的指令高速缓存器的微处理器内使用的分支预测系统。分支预测表（BPT）的每个条目包括标识公共高速缓存行中的至少一个其他指令是否包含分支的值。该值在本文中称为多B位值。通过分支预测逻辑检查多个B比特值，同时执行一个分支预测以确定是否可以针对同一高速缓存行内的另一个分支启动第二分支预测。在一个实现中，在命中之后检查一个BPT条目的多个B位。开始生成命中的条目的分支预测。同时，如果设置了第一个条目的多个B位，则BPT被重新访问以搜索与同一高速缓存行内的另一个指令相对应的条目。如果找到第二个条目，则启动辅助分支预测。最终输出第一个分支预测。如果第一分支预测未被采用，则在下一个时钟周期期间输出第二分支预测。如果采用第一分支预测，那么第二分支预测可能因不需要而中止。描述本发明的方法和设备实施例。

20. 发明授权

US08352685B2 Combining write buffer with dynamically adjustable flush metrics 有权
标题翻译：将写入缓冲区与动态可调整的flush指标相结合
公开(公告)号：US08352685B2
公开(公告)日：2013-01-08
申请号：US12860505
申请日：2010-08-20
申请人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
发明人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0891 , G06F12/0804
摘要： In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.
摘要翻译：在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为折叠。折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

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