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11. 发明申请

US20050277258A1 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US20050277258A1
公开(公告)日：2005-12-15
申请号：US10940707
申请日：2004-09-15
申请人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
发明人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L27/10 , H01L27/105
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L27/105 , H01L27/1052
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：在晶体管的栅极结构和扩散区上形成薄的氮化物绝缘层; 形成第一绝缘层，然后将其平坦化以暴露栅极结构上的氮化物绝缘层; 蚀刻穿过第一绝缘层以形成接触孔的第一部分; 在所述接触孔的所述第一部分中形成接触的第一部分; 形成第二绝缘层; 蚀刻穿过第二绝缘层以形成接触孔的第二部分; 以及在接触孔的第二部分中形成接触的第二部分。用于形成导电接触的两级蚀刻工艺有效地防止了字线和位线之间的过蚀刻和短路。

12. 发明申请

US20050106887A1 Method for formimg contact holes 有权
标题翻译：形成接触孔的方法
公开(公告)号：US20050106887A1
公开(公告)日：2005-05-19
申请号：US10783467
申请日：2004-02-20
申请人： Yi-Nan Chen , Tse-Yao Huang , Hui-Min Mao
发明人： Yi-Nan Chen , Tse-Yao Huang , Hui-Min Mao
IPC分类号： H01L21/28 , H01L21/283 , H01L21/302 , H01L21/461 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76816 , H01L21/76897
摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.
摘要翻译：一种形成接触孔的方法。提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。在栅极结构上形成绝缘层，并填充在栅极结构之间。使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出门盖层。在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。去除保护性间隔物。

13. 发明申请

US20060127680A1 Multi-layer hard mask structure for etching deep trench in substrate 有权
公开(公告)号：US20060127680A1
公开(公告)日：2006-06-15
申请号：US11348626
申请日：2006-02-07
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B32B17/06 , B32B9/00
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

14. 发明授权

US07029753B2 Multi-layer hard mask structure for etching deep trench in substrate 有权
标题翻译：用于蚀刻衬底深沟槽的多层硬掩模结构
公开(公告)号：US07029753B2
公开(公告)日：2006-04-18
申请号：US10727790
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B23B17/06
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
摘要翻译：一种用于蚀刻衬底中的深沟槽的方法。形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。去除多层硬掩模结构。

15. 发明申请

US20050042871A1 Multi-layer hard mask structure for etching deep trench in substrate 有权
标题翻译：用于蚀刻衬底深沟槽的多层硬掩模结构
公开(公告)号：US20050042871A1
公开(公告)日：2005-02-24
申请号：US10727790
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： C03C15/00 , H01L21/033 , H01L21/308 , H01L21/8242 , B32B17/06 , H01L21/302 , H01L21/461
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
摘要翻译：一种用于蚀刻衬底中的深沟槽的方法。形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。去除多层硬掩模结构。

16. 发明授权

US08476764B2 Bonding pad structure for semiconductor devices 有权
标题翻译：用于半导体器件的接合焊盘结构
公开(公告)号：US08476764B2
公开(公告)日：2013-07-02
申请号：US13235491
申请日：2011-09-18
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05085 , H01L2224/05095 , H01L2224/05624
摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
摘要翻译：焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及多个通孔插塞，其设置在焊盘形成区域的环形区域内的最上层的IMD层中，其中通孔插塞不形成在焊盘形成区域的中心区域中。

17. 发明授权

US07056832B2 Deep trench self-alignment process for an active area of a partial vertical cell 有权
标题翻译：用于部分垂直单元的活动区域的深沟槽自对准过程
公开(公告)号：US07056832B2
公开(公告)日：2006-06-06
申请号：US10622965
申请日：2003-07-18
申请人： Ming-Cheng Chang , Yi-Nan Chen , Tse-Yao Huang
发明人： Ming-Cheng Chang , Yi-Nan Chen , Tse-Yao Huang
IPC分类号： H01L21/302
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.
摘要翻译：用于部分垂直单元的活动区域的深沟槽自对准过程。提供具有两个深沟槽的半导体衬底。在每个深沟槽中形成深沟槽电容器，并在其上形成隔离层。每个沟槽填充有掩模层。在深沟槽之间的半导体衬底上形成光致抗蚀剂层，并且光致抗蚀剂层部分地覆盖掩模层。使用光致抗蚀剂层和掩模层作为掩模，将半导体衬底蚀刻成比隔离层低。去除光致抗蚀剂层和掩模层，使得深沟槽之间的柱状半导体衬底用作有效区域。

18. 发明申请

US20050147926A1 Method for processing photoresist 审中-公开
标题翻译：光刻胶的处理方法
公开(公告)号：US20050147926A1
公开(公告)日：2005-07-07
申请号：US10749590
申请日：2004-01-02
申请人： Hsiu-Chun Lee , Tse-Yao Huang , Yi-Nan Chen , Chih-Ta Wang
发明人： Hsiu-Chun Lee , Tse-Yao Huang , Yi-Nan Chen , Chih-Ta Wang
IPC分类号： G03F7/00 , G03F7/16 , G03F7/36 , G03F7/40
CPC分类号： G03F7/168 , G03F7/40 , G03F7/405
摘要： Disclosed is a method for processing photoresist. The method of the present invention performs Ar plasma process to the photoresist after or before the photoreisist is formed into a pattern to make the photoresist dense.
摘要翻译：公开了一种处理光致抗蚀剂的方法。本发明的方法在光电导体形成图案之后或之后对光致抗蚀剂进行Ar等离子体处理以使光致抗蚀剂致密。

19. 发明申请

US20050118531A1 METHOD FOR CONTROLLING CRITICAL DIMENSION BY UTILIZING RESIST SIDEWALL PROTECTION 审中-公开
标题翻译：通过利用电阻板保护来控制关键尺寸的方法
公开(公告)号：US20050118531A1
公开(公告)日：2005-06-02
申请号：US10707259
申请日：2003-12-02
申请人： Hsiu-Chun Lee , Tse-Yao Huang , Yi-Nan Chen
发明人： Hsiu-Chun Lee , Tse-Yao Huang , Yi-Nan Chen
IPC分类号： G03F7/00 , G03F7/36 , H01L21/027 , H01L21/3213
CPC分类号： H01L21/0274 , H01L21/32137 , H01L21/32139
摘要： A method for controlling line width critical dimension is disclosed. A semiconductor layer is deposited on a substrate. A cap layer is formed on the semiconductor layer. A patterned photoresist is formed on the cap layer. The patterned photoresist has a top surface and vertical sidewalls. A silicon thin film is selectively sputtered on the top surface and vertical sidewalls of the patterned photoresist, but not on the cap layer. The silicon thin film, which has a thickness: x above the top surface and a thickness: y on the sidewalls of the patterned photoresist, wherein xx
摘要翻译：公开了一种用于控制线宽临界尺寸的方法。在衬底上沉积半导体层。在半导体层上形成覆盖层。在盖层上形成图案化的光致抗蚀剂。图案化的光致抗蚀剂具有顶表面和垂直侧壁。硅薄膜在图案化光致抗蚀剂的顶表面和垂直侧壁上被选择性溅射，但不在盖层上。硅薄膜的厚度x高于顶表面，图案化光致抗蚀剂的侧壁上的厚度为：y，其中xx <，用于保护图案化的光致抗蚀剂。使用硅薄膜和图案化的光致抗蚀剂作为蚀刻掩模，封盖层被各向异性蚀刻，从而将光刻胶图案转印到盖层。最后，使用盖层作为蚀刻掩模，蚀刻半导体层。

20. 发明申请

US20050085025A1 METHOD OF FORMING GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20050085025A1
公开(公告)日：2005-04-21
申请号：US10605678
申请日：2003-10-17
申请人： Jin-Tau Huang , Chung-Peng Hao , Yi-Nan Chen , Tse-Yao Huang
发明人： Jin-Tau Huang , Chung-Peng Hao , Yi-Nan Chen , Tse-Yao Huang
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/28061
摘要： A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a suicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.
摘要翻译：一种形成栅极结构的方法。首先，提供基板，并且在基板上连续地形成栅氧化层，多晶硅层，硅化物层和盖层。然后，进行蚀刻处理以蚀刻覆盖层，硅化物层和多晶硅层的一部分，并停留在多晶硅层上以形成堆叠栅极。此后，去除暴露在堆叠栅极的侧壁上的硅化物层的一部分以形成凹陷。沉积钝化层以填充凹部。除去堆叠栅结构的侧壁外的剩余多晶硅层和栅氧化层。

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