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11. 发明申请

US20100168895A1 MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM 审中-公开
标题翻译：掩模验证方法，制造半导体器件的方法和计算机可读介质
公开(公告)号：US20100168895A1
公开(公告)日：2010-07-01
申请号：US12561626
申请日：2009-09-17
申请人： Hiromitsu MASHITA , Fumiharu Nakajima , Toshiya Kotani , Hidefumi Mukai , Issui Aiba
发明人： Hiromitsu MASHITA , Fumiharu Nakajima , Toshiya Kotani , Hidefumi Mukai , Issui Aiba
IPC分类号： G05B13/04 , G06F17/50
CPC分类号： G03F7/705 , G03F1/36
摘要： A mask verification method includes setting optical parameters, verifying whether a pattern, which is obtained when a mask pattern other than a reference pattern of patterns on a mask is transferred on a substrate with use of the set optical parameters, satisfies dimensional specifications, and varying, when the pattern which is obtained when the mask pattern is transferred on the substrate is determined to fail to satisfy the dimensional specifications, the optical parameters at the time of transfer such that the pattern, which is obtained when the reference pattern is transferred on the substrate, satisfies a target dimensional condition, and verifying whether a pattern, which is obtained when the mask pattern other than the reference pattern of the patterns on the mask is transferred on the substrate with use of the varied optical parameters, satisfies the dimensional specifications.
摘要翻译：掩模验证方法包括设置光学参数，验证当掩模上的图案的参考图案之外的掩模图案使用所设置的光学参数在基板上转印时获得的图案是否满足尺寸规格，并且变化当将掩模图案转印到基板上时获得的图案被确定为不能满足尺寸规格，转印时的光学参数使得当在基板上转印参考图案时获得的图案基板，满足目标尺寸条件，并且验证当使用变化的光学参数在掩模上的图案的参考图案之外的掩模图案被转印到基板上时获得的图案是否满足尺寸规格。

12. 发明申请

US20100081265A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100081265A1
公开(公告)日：2010-04-01
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

13. 发明授权

US07925090B2 Method of determining photo mask, method of manufacturing semiconductor device, and computer program product 失效
标题翻译：确定光掩模的方法，制造半导体器件的方法以及计算机程序产品
公开(公告)号：US07925090B2
公开(公告)日：2011-04-12
申请号：US11601797
申请日：2006-11-20
申请人： Toshiya Kotani , Kazuya Fukuhara , Kyoko Izuha
发明人： Toshiya Kotani , Kazuya Fukuhara , Kyoko Izuha
IPC分类号： G06K9/34
CPC分类号： G03F7/70441
摘要： A method of determining a photo mask, includes specifying a mask pattern for a photo mask for a first exposure apparatus, specifying a plurality of exposure conditions allowed to be set for a second exposure apparatus, predicting a projection image of the mask pattern to be projected on a substrate by the second exposure apparatus, for each of the exposure conditions, predicting a processed pattern to be formed on a substrate surface on the basis of the projection image, for each of the exposure conditions, determining whether or not the processed pattern meets a predetermined condition for each of the exposure conditions, and determining that the photo mask is applicable to the second exposure apparatus if the processed pattern meets the predetermined condition for at least one of the exposure conditions.
摘要翻译：一种确定光掩模的方法包括：为第一曝光装置指定用于光掩模的掩模图案，指定允许为第二曝光装置设置的多个曝光条件，预测要投影的掩模图案的投影图像在第二曝光装置的基板上，对于每个曝光条件，对于每个曝光条件，基于投影图像预测要在基板表面上形成的处理图案，确定处理图案是否满足对于每个曝光条件的预定条件，并且如果处理的图案满足至少一个曝光条件的预定条件，则确定光掩模适用于第二曝光装置。

14. 发明申请

US20070130560A1 Method of determining photo mask, method of manufacturing semiconductor device, and computer program product 失效
标题翻译：确定光掩模的方法，制造半导体器件的方法以及计算机程序产品
公开(公告)号：US20070130560A1
公开(公告)日：2007-06-07
申请号：US11601797
申请日：2006-11-20
申请人： Toshiya Kotani , Kazuya Fukuhara , Kyoko Izuha
发明人： Toshiya Kotani , Kazuya Fukuhara , Kyoko Izuha
IPC分类号： G06F17/50
CPC分类号： G03F7/70441
摘要： A method of determining a photo mask, includes specifying a mask pattern for a photo mask for a first exposure apparatus, specifying a plurality of exposure conditions allowed to be set for a second exposure apparatus, predicting a projection image of the mask pattern to be projected on a substrate by the second exposure apparatus, for each of the exposure conditions, predicting a processed pattern to be formed on a substrate surface on the basis of the projection image, for each of the exposure conditions, determining whether or not the processed pattern meets a predetermined condition for each of the exposure conditions, and determining that the photo mask is applicable to the second exposure apparatus if the processed pattern meets the predetermined condition for at least one of the exposure conditions.
摘要翻译：一种确定光掩模的方法包括：为第一曝光装置指定用于光掩模的掩模图案，指定允许为第二曝光装置设置的多个曝光条件，预测要投影的掩模图案的投影图像在第二曝光装置的基板上，对于每个曝光条件，对于每个曝光条件，基于投影图像预测要在基板表面上形成的处理图案，确定处理图案是否满足对于每个曝光条件的预定条件，并且如果处理的图案满足至少一个曝光条件的预定条件，则确定光掩模适用于第二曝光装置。

15. 发明申请

US20120070985A1 EXPOSURE METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：曝光方法和制造半导体器件的方法
公开(公告)号：US20120070985A1
公开(公告)日：2012-03-22
申请号：US13233971
申请日：2011-09-15
申请人： Takaki Hashimoto , Kazuya Fukuhara , Toshiya Kotani , Yasunobu Kai
发明人： Takaki Hashimoto , Kazuya Fukuhara , Toshiya Kotani , Yasunobu Kai
IPC分类号： H01L21/768 , G03B27/32
CPC分类号： H01L27/0207 , G03F1/50 , G03F7/70325 , H01L21/0274 , H01L21/31144 , H01L27/11519 , H01L27/11524
摘要： According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.
摘要翻译：根据一个实施例，公开了曝光方法。该方法可以包括通过照明将光照射到光掩模。该方法可以包括通过透镜会聚从光掩模发射的衍射光束。此外，该方法可以包括在曝光表面上成像多个点图像。在光掩模上，在由非正交单元矢量表示的格点处形成光透射区域，在照明中，设定发光区域，使得三个以上的衍射光束通过与瞳孔中心等距的位置的镜头。

16. 发明授权

US08122385B2 Mask pattern correcting method 有权
标题翻译：掩模图案校正方法
公开(公告)号：US08122385B2
公开(公告)日：2012-02-21
申请号：US12129167
申请日：2008-05-29
申请人： Kazuya Fukuhara , Tatsuhiko Higashiki , Toshiya Kotani , Satoshi Tanaka , Takashi Sato , Akiko Mimotogi , Masaki Satake
发明人： Kazuya Fukuhara , Tatsuhiko Higashiki , Toshiya Kotani , Satoshi Tanaka , Takashi Sato , Akiko Mimotogi , Masaki Satake
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.
摘要翻译：在基于模型的OPC中，使用光学图像强度模拟器对每个掩模图案进行适当的掩模校正，将掩模图案划分为子区域，并且根据每个子区域中的图案的内容来改变光学图像强度模拟模型。当掩模图案的最小尺寸小于在曝光波长附近设置的特定阈值时，使用高精度模型计算该区域，并且使用高速模型来计算其它区域。

17. 发明授权

US07716628B2 System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects 失效
标题翻译：考虑到光学邻近效应，产生掩模数据，曝光掩模和半导体器件的系统，方法和程序
公开(公告)号：US07716628B2
公开(公告)日：2010-05-11
申请号：US11298840
申请日：2005-12-12
申请人： Satoshi Tanaka , Kazuya Fukuhara , Toshiya Kotani
发明人： Satoshi Tanaka , Kazuya Fukuhara , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A system for generating mask data includes an extracting module extracting a block necessary to correct process proximity effects as a wide correction area from a plurality of blocks by comparing parameter, a wide correction data generator generating wide correction data to make the correction applied to the wide correction area, and a mask data generator generating mask data by applying the wide correction data to the wide correction area.
摘要翻译：一种用于生成掩模数据的系统，包括提取模块，通过比较参数，从多个块中提取校正过程邻近效应所需的块作为宽的校正区域;广泛的校正数据生成器，产生宽的校正数据，使校正应用于宽校正区域，以及掩模数据生成器，通过将宽校正数据应用于宽校正区域来生成掩模数据。

18. 发明申请

US20060129967A1 System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects 失效
标题翻译：考虑到光学邻近效应，产生掩模数据，曝光掩模和半导体器件的系统，方法和程序
公开(公告)号：US20060129967A1
公开(公告)日：2006-06-15
申请号：US11298840
申请日：2005-12-12
申请人： Satoshi Tanaka , Kazuya Fukuhara , Toshiya Kotani
发明人： Satoshi Tanaka , Kazuya Fukuhara , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A system for generating mask data includes an extracting module extracting a block necessary to correct process proximity effects as a wide correction area from a plurality of blocks by comparing parameter, a wide correction data generator generating wide correction data to make the correction applied to the wide correction area, and a mask data generator generating mask data by applying the wide correction data to the wide correction area.
摘要翻译：一种用于生成掩模数据的系统，包括提取模块，通过比较参数，从多个块中提取校正过程邻近效应所需的块作为宽的校正区域;广泛的校正数据生成器，产生宽的校正数据，使校正应用于宽校正区域，以及掩模数据生成器，通过将宽校正数据应用于宽校正区域来生成掩模数据。

19. 发明授权

US08142961B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 有权
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US08142961B2
公开(公告)日：2012-03-27
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

20. 再颁专利

USRE42302E1 Method for making a design layout and mask 有权
标题翻译：制作设计布局和面具的方法
公开(公告)号：USRE42302E1
公开(公告)日：2011-04-19
申请号：US11905862
申请日：2007-10-04
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5081
摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则预定条件。

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