专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050202607A1 Method of forming FinFET gates without long etches 有权
标题翻译：在没有长时间刻蚀的情况下形成FinFET栅极的方法
公开(公告)号：US20050202607A1
公开(公告)日：2005-09-15
申请号：US10798907
申请日：2004-03-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hofak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hofak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795 , H01L29/7831
摘要： A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.
摘要翻译：用于形成用于FinFET的栅极的方法使用一系列选择性沉积的侧壁与其它牺牲层一起形成可以准确可靠地形成栅极的空腔。该技术避免了长时间的定向蚀刻步骤，以形成使用常规技术有助于形成FinFET的困难的栅极的临界尺寸。特别地，首先在硅片上沉积可以精确地生长侧壁的牺牲种子层。一旦牺牲种子层被蚀刻掉，侧壁可以被另一个一次性层包围。蚀刻侧壁将导致跨过翅片形成的空腔，然后栅极导体材料可以沉积在这些空腔内。因此，通过避免沿翅片的整个高度的长方向蚀刻，可以精确地控制所得FinFET栅极的高度和厚度。

12. 发明申请

US20050130341A1 Selective synthesis of semiconducting carbon nanotubes 失效
标题翻译：半导体碳纳米管的选择性合成
公开(公告)号：US20050130341A1
公开(公告)日：2005-06-16
申请号：US10732951
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： B82B3/00 , C01B31/02 , C30B25/02 , C30B29/02 , C30B29/60 , H01L29/15 , H01L29/786 , H01L51/30 , H01L21/336
CPC分类号： H01L51/0512 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/22 , C01B2202/34 , C30B25/02 , C30B29/02 , C30B29/605 , H01L51/0048 , Y10S977/854
摘要： Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.
摘要翻译：从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构选择半导体碳纳米管的方法。在初始生长阶段之后，改变承载导电碳纳米管的合成位点，以在这些特定合成位点停止合成，从而停止导电碳纳米管的延长。具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。

13. 发明申请

US20060008927A1 Dual gated finfet gain cell 有权
标题翻译：双门控finfet增益单元
公开(公告)号：US20060008927A1
公开(公告)日：2006-01-12
申请号：US11221118
申请日：2005-09-07
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
摘要翻译：用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。第一栅电极与存储装置电耦合。第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。当门控时，电流的大小取决于存储设备存储的电量。

14. 发明申请

US20050202322A1 Methods of forming alternating phase shift masks having improved phase-shift tolerance 失效
标题翻译：形成具有改进的相移公差的交替相移掩模的方法
公开(公告)号：US20050202322A1
公开(公告)日：2005-09-15
申请号：US10798908
申请日：2004-03-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00
CPC分类号： G03F1/30
摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.
摘要翻译：用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。图案层从手柄晶片转移到掩模板。相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

15. 发明申请

US20050189655A1 Integrated circuit chip utilizing carbon nanotube composite interconnection vias 有权
标题翻译：使用碳纳米管复合互连通孔的集成电路芯片
公开(公告)号：US20050189655A1
公开(公告)日：2005-09-01
申请号：US10787640
申请日：2004-02-26
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell , Stanislav Polonsky
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell , Stanislav Polonsky
IPC分类号： H01L21/285 , H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： B82Y10/00 , H01L21/28562 , H01L21/76877 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.
摘要翻译：集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。优选地，导电路径包括在导电层之间延伸的通孔。优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔有铜的腔。然后在通孔上形成下一导电层。

16. 发明申请

US20050129948A1 Methods and structures for promoting stable synthesis of carbon nanotubes 有权
标题翻译：促进碳纳米管稳定合成的方法和结构
公开(公告)号：US20050129948A1
公开(公告)日：2005-06-16
申请号：US10733974
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hotak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hotak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： C01B31/02 , B32B9/00 , B82B3/00 , C01B31/00 , H01J1/304 , H01J9/02 , H01L29/04
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y40/00 , C01B32/162 , C01B2202/06 , C01B2202/22 , C01B2202/34 , H01J1/3044 , H01J2201/30469 , Y10S977/742 , Y10S977/84 , Y10S977/842 , Y10S977/843 , Y10T428/30
摘要： A method for synthesizing carbon nanotubes and structure formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.
摘要翻译：一种合成碳纳米管的方法及由此形成的结构。该方法包括在由第一基板支撑的多个合成位置上形成碳纳米管，中断纳米管合成，将每个碳纳米管的自由端安装到第二基板上，以及去除第一基板。每个碳纳米管被其中一个合成位点封盖，生长反应物可以随时进入。由于碳纳米管在恢复纳米管合成过程中延长，所以进入合成位点仍未被排除。

17. 发明申请

US20050106472A1 ALTERNATING PHASE MASK BUILT BY ADDITIVE FILM DEPOSITION 失效
标题翻译：通过添加膜沉积来替代相位掩模
公开(公告)号：US20050106472A1
公开(公告)日：2005-05-19
申请号：US10707009
申请日：2003-11-13
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger, III , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger, III , Peter Mitchell , Larry Nesbit
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , C23F3/00 , G03C5/00 , G03F1/00 , G03F9/00
CPC分类号： G03F1/30 , G03F1/54 , G03F1/68
摘要： The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the etch stop layer to expose areas of the transparent substrate. Next, the invention forms a mask on the non-transparent film to protect selected areas of the transparent substrate and forms a phase shift oxide on exposed areas of the transparent substrate. Subsequently, the mask is removed and the phase shift oxide is polished down to the etch stop layer, after which the etch stop layer is removed.
摘要翻译：本发明提供一种形成相移掩模的方法和所得到的相移掩模。该方法在透明基板上形成不透明的薄膜，并在非透明薄膜上形成蚀刻停止层。本发明使用蚀刻停止层来图案化非透明膜以暴露透明基底的区域。接下来，本发明在非透明膜上形成掩模，以保护透明基板的选定区域，并在透明基板的曝光区域上形成相移氧化物。随后，去除掩模并将相移氧化物抛光到蚀刻停止层，之后去除蚀刻停止层。

18. 发明申请

US20070184647A1 Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes 审中-公开
标题翻译：集成电路芯片利用由碳纳米管形成的定向圆柱形空隙的介电层
公开(公告)号：US20070184647A1
公开(公告)日：2007-08-09
申请号：US11735988
申请日：2007-04-16
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/4763
CPC分类号： B82Y10/00 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.
摘要翻译：集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。优选地，通过首先形成垂直于集成电路晶片的表面的多个相对长的薄碳纳米管，在围绕碳纳米管的表面上沉积常规电介质，然后除去碳纳米管以产生空隙来形成空隙。由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。用于导体的电介质中形成的凹陷衬有非共形绝缘膜以密封空隙。使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

19. 发明申请

US20060022221A1 Integrated circuit chip utilizing oriented carbon nanotube conductive layers 失效
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20060022221A1
公开(公告)日：2006-02-02
申请号：US10901858
申请日：2004-07-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L29/768
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

20. 发明申请

US20050127466A1 Wrap-around gate field effect transistor 有权
标题翻译：环绕栅场效应晶体管
公开(公告)号：US20050127466A1
公开(公告)日：2005-06-16
申请号：US10732958
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/334 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/76 , H01L29/00
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/78645 , H01L29/78648
摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.
摘要翻译：形成具有环绕，垂直排列的双栅电极的场效应晶体管。从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。第二次回蚀将栅极导体材料的一部分移除第二距离。第一和第二距离之间的差异定义了最终设备的栅极长度。剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式