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11. 发明授权

US08401384B2 Optical access system, optical switching unit and optical line terminal 有权
标题翻译：光接入系统，光交换单元和光线路终端
公开(公告)号：US08401384B2
公开(公告)日：2013-03-19
申请号：US12503884
申请日：2009-07-16
申请人： Koji Wakayama , Hiroki Ikeda , Michitaka Okuno , Kenichi Sakamoto
发明人： Koji Wakayama , Hiroki Ikeda , Michitaka Okuno , Kenichi Sakamoto
IPC分类号： H04J14/00 , H04B10/00
CPC分类号： H04Q11/0067 , H04Q2011/0045 , H04Q2011/0064
摘要： Provided is an optical access system, including: an optical line terminal, a plurality of optical network units and an optical switching unit. The optical line terminal sends to the optical switching unit a control frame including a switching time when the optical switching unit is to make a switch from one of the optical communication paths between the optical line terminal and the plurality of optical network units to another, and an identifier of an optical communication path to which the switch is made in order to switch the optical communication paths between the optical line terminal and the plurality of optical network units. The optical switching unit switches the optical communication paths between the optical line terminal and the plurality of optical network units based on the switching time and the identifier of the optical communication path after switching which are included in the control frame.
摘要翻译：提供一种光接入系统，包括：光线路终端，多个光网络单元和光交换单元。光线路终端向光交换单元发送包括切换时间的控制帧，当光交换单元从光线路终端与多个光网络单元之间的光通信路径之一进行切换时，切换时间为为了切换光线路终端与多个光网络单元之间的光通信路径而进行交换的光通信路径的标识符。光切换单元基于包括在控制帧中的切换时间和切换后的光通信路径的标识符，切换光线路终端与多个光网络单元之间的光通信路径。

12. 发明申请

US20090198864A1 NETWORK SWITCH AND METHOD OF SWITCHING IN NETWORK 有权
标题翻译：网络切换和网络切换方法
公开(公告)号：US20090198864A1
公开(公告)日：2009-08-06
申请号：US12276677
申请日：2008-11-24
申请人： Isao Kimura , Mitsuo Yamamoto , Michitaka Okuno
发明人： Isao Kimura , Mitsuo Yamamoto , Michitaka Okuno
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that transfer unit data in a specified format; a receiving side transfer unit that transfers data received from a network to the plurality of crossbar switches in the unit data basis; and a plurality of transmitting side transfer units that transmit data transferred from the plurality of crossbar switches to the network. The receiving side transfer sets a consecutive serial number to the unit data in transfer sequence, and distributes the unit data to the plurality of crossbar switches. Each of the plurality of transmitting side transfer units has a plurality of queues for the respective crossbar switches that stores the transferred unit data, and extracts the unit data with smallest serial number of the unit data stored in the queues when all of the queues store the unit data.
摘要翻译：提供一种具有多个交叉开关的网络开关，其可用于抑制电路规模的增加。网络交换机具有：以指定格式传送单元数据的多个交叉开关; 接收侧传送单元，以单元数据为基础将从网络接收的数据传送到所述多个交叉开关; 以及多个发送侧传送单元，其将从多个交叉开关传送的数据发送到网络。接收侧传送以传输顺序将连续的序列号设置为单元数据，并将单元数据分配给多个交叉开关。多个发送侧传送单元中的每一个具有用于存储传送的单元数据的各个交叉开关的多个队列，并且当所有队列存储在队列中时提取存储在队列中的单元数据的最小序列号的单元数据单位数据。

13. 发明申请

US20060253606A1 Packet transfer apparatus 失效
公开(公告)号：US20060253606A1
公开(公告)日：2006-11-09
申请号：US11411023
申请日：2006-04-26
申请人： Michitaka Okuno
发明人： Michitaka Okuno
IPC分类号： G06F15/173
CPC分类号： H04L45/54 , H04L45/02 , H04L45/60 , H04L45/742
摘要： In a packet transfer apparatus, a larger number of entries can be registered to routing tables without increasing the overall memory volume required for the routing tables to record transfer information of packets. A routing table search is conducted at a high speed. Each line card of the packet transfer apparatus includes two kinds of routing tables, i.e., first and second routing tables having mutually different functions. The first routing tables are local routing tables to record frequently used transfer information in groups. The second routing tables are shared distributed routing tables and record the transfer information in a distributed way without an overlapped part of the transfer information between the line cards. The sum of the distributed transfer information matches the overall transfer information kept in the packet transfer apparatus.

14. 发明申请

US20050074005A1 Network-processor accelerator 失效
标题翻译：网络处理器加速器
公开(公告)号：US20050074005A1
公开(公告)日：2005-04-07
申请号：US10956089
申请日：2004-10-04
申请人： Michitaka Okuno
发明人： Michitaka Okuno
IPC分类号： H04L12/701 , G11C15/00 , H04L12/747 , H04L12/773 , H04L12/56
CPC分类号： H04L45/00 , H04L45/60 , H04L49/3009
摘要： In order to perform cache processing for the received packets, a network apparatus is provided with a network-processor accelerator for caching the process result of a network processor. Accordingly, the network apparatus of the present invention ensuring higher packet-processing throughput can be realized by improving the packet-processing throughput without increase in the chip area, increase in the power consumption, and shortage in an external connected memory bandwidth.
摘要翻译：为了对接收到的分组执行高速缓存处理，网络设备具有用于缓存网络处理器的处理结果的网络处理器加速器。因此，可以通过提高分组处理吞吐量而不增加芯片面积，增加功耗以及外部连接的存储器带宽的不足来实现确保更高分组处理吞吐量的本发明的网络装置。

15. 发明授权

US08095721B2 Network switch and method of switching in network 有权
标题翻译：网络切换和网络切换方式
公开(公告)号：US08095721B2
公开(公告)日：2012-01-10
申请号：US12276677
申请日：2008-11-24
申请人： Isao Kimura , Mitsuo Yamamoto , Michitaka Okuno
发明人： Isao Kimura , Mitsuo Yamamoto , Michitaka Okuno
IPC分类号： G06F13/14 , H04L12/00
CPC分类号： G06F13/4022
摘要： A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that transfer unit data in a specified format; a receiving side transfer unit that transfers data received from a network to the plurality of crossbar switches in the unit data basis; and a plurality of transmitting side transfer units that transmit data transferred from the plurality of crossbar switches to the network. The receiving side transfer sets a consecutive serial number to the unit data in transfer sequence, and distributes the unit data to the plurality of crossbar switches. Each of the plurality of transmitting side transfer units has a plurality of queues for the respective crossbar switches that stores the transferred unit data, and extracts the unit data with smallest serial number of the unit data stored in the queues when all of the queues store the unit data.
摘要翻译：提供一种具有多个交叉开关的网络开关，其可用于抑制电路规模的增加。网络交换机具有：以指定格式传送单元数据的多个交叉开关; 接收侧传送单元，以单元数据为基础将从网络接收的数据传送到所述多个交叉开关; 以及多个发送侧传送单元，其将从多个交叉开关传送的数据发送到网络。接收侧传送以传输顺序将连续的序列号设置为单元数据，并将单元数据分配给多个交叉开关。多个发送侧传送单元中的每一个具有用于存储传送的单元数据的各个交叉开关的多个队列，并且当所有队列存储在队列中时提取存储在队列中的单元数据的最小序列号的单位数据单位数据。

16. 发明授权

US06970999B2 Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters 失效
标题翻译：使用多个分配的计数器计数指令表的等待时间，刷新，补充和指令执行
公开(公告)号：US06970999B2
公开(公告)日：2005-11-29
申请号：US10210415
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F9/38 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855
摘要： A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.
摘要翻译：一种用于分析处理器中每条指令（CPI）性能的循环的方法和系统。完成表对应于要由处理器处理的组中的指令。一个空的完成表表明有一些类型的灾难导致表冲洗。当表为空时，位于处理器中的性能监视单元（PMU）中的性能监视计数器（PMC）会计数表为空的时钟周期数。优选地，根据完成表为空的原因，使用单独的PMC。第二个PMC同样计算重新填充空完成表的时钟周期数。第三个PMC计算在完成表中实际执行指令花费的时钟周期数。 PMC中的信息可用于评估CPI性能下降的真正原因。

17. 发明授权

US08116305B2 Multi-plane cell switch fabric system 有权
标题翻译：多平面单元交换矩阵系统
公开(公告)号：US08116305B2
公开(公告)日：2012-02-14
申请号：US12410655
申请日：2009-03-25
申请人： Michitaka Okuno , Mitsuo Yamamoto , Isao Kimura
发明人： Michitaka Okuno , Mitsuo Yamamoto , Isao Kimura
IPC分类号： H04L12/50 , H04Q11/00
CPC分类号： H04L49/3072 , H04L49/1523
摘要： A multi-plane cell switch fabric system prevents a decrease of the effective switching capacity when switching the variable-length packets. Distribution units classify input variable-length packets for each address, arranges the packets by a first division length unit, divides the packets into fixed-length cell payloads by a second division length unit that is an integer multiple being twice or more as large as the first division length unit, and forms a fixed-length cell by providing destination information, a source ID, a sequential number, and packet head tail information to each of the cell payloads. The cells are distributed to all the switching units one by one whenever the cells are collected to be the same number as the plural switching units. The reordering units classify the cells, reorder the sequential number in an original order, and reassemble the packets by the packet head tail information of the cell.
摘要翻译：多层小区交换矩阵系统在切换可变长度分组时可以防止有效切换容量的降低。分配单元为每个地址分类输入可变长度分组，按照第一分区长度单位排列分组，将分组划分为固定长度的小区有效载荷，第二分割长度单位是整数倍的两倍或更多倍并且通过向每个小区有效载荷提供目的地信息，源ID，序列号和分组头尾信息来形成固定长度小区。每当这些单元被收集成与多个开关单元相同的数量时，这些单元一个接一个地分配给所有的开关单元。重新排序单元对单元进行分类，以原始顺序重新排列顺序号，并通过单元的分组头尾信息重新组合分组。

18. 发明授权

US07907606B2 Multi-plane cell switch fabric system 有权
标题翻译：多平面单元交换矩阵系统
公开(公告)号：US07907606B2
公开(公告)日：2011-03-15
申请号：US12273579
申请日：2008-11-19
申请人： Michitaka Okuno , Mitsuo Yamamoto , Isao Kimura
发明人： Michitaka Okuno , Mitsuo Yamamoto , Isao Kimura
IPC分类号： H04Q11/00 , H04L12/56
CPC分类号： H04L49/1523 , H04L49/252 , H04L49/3009 , H04L49/3072 , H04L49/503 , H04L49/552
摘要： Cells which arrive in random sequence from the asynchronously operating exchange parts are restored into the original by a small amount of hardware. Distributing parts as inputs of a switch fabric manage serial numbers continuous for each destination. The distributing part divides an inputted variable length packet into fixed length cells, adds serial numbers corresponding to destinations to the cells, and outputs the cells to the exchange parts. The respective exchange parts deliver the cells to the objected destinations. Alignment parts as outputs of the switch fabric classify the reception cells by the number of the distributing part, and compare an expected serial number managed by the alignment part with a serial number of the destination (alignment part) of the reception cell. An identical one is stored in an aligned FIFO queue, and cells of from a packet start cell to a packet end cell are taken out.
摘要翻译：从异步操作的交换部件以随机顺序到达的单元由少量硬件恢复为原始。分配部分作为交换机结构的输入管理每个目的地连续的序列号。分配部将输入的可变长度分组划分为固定长度的小区，将与目的地对应的序列号添加到小区，并将该小区输出到交换部。相应的交换部分将单元传送到被反对的目的地。作为交换结构的输出的对齐部分将接收信元分配到分发部分的数量，并将对准部分管理的期望序列号与接收信元的目的地（对准部分）的序列号进行比较。相同的存储在对齐的FIFO队列中，并且从数据包起始单元到分组末端单元的单元被取出。

19. 发明授权

US07440457B2 Network-processor accelerator 失效
标题翻译：网络处理器加速器
公开(公告)号：US07440457B2
公开(公告)日：2008-10-21
申请号：US10956089
申请日：2004-10-04
申请人： Michitaka Okuno
发明人： Michitaka Okuno
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/60 , H04L49/3009
摘要： In order to perform cache processing for the received packets, a network apparatus is provided with a network-processor accelerator for caching the process result of a network processor. Accordingly, the network apparatus of the present invention ensuring higher packet-processing throughput can be realized by improving the packet-processing throughput without increase in the chip area, increase in the power consumption, and shortage in an external connected memory bandwidth.
摘要翻译：为了对接收到的分组执行高速缓存处理，网络设备具有用于缓存网络处理器的处理结果的网络处理器加速器。因此，可以通过提高分组处理吞吐量而不增加芯片面积，增加功耗以及外部连接的存储器带宽的不足来实现确保更高分组处理吞吐量的本发明的网络装置。

20. 发明申请

US20060098675A1 Traffic control method for network equipment 失效
标题翻译：网络设备的流量控制方法
公开(公告)号：US20060098675A1
公开(公告)日：2006-05-11
申请号：US11195702
申请日：2005-08-03
申请人： Michitaka Okuno
发明人： Michitaka Okuno
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9036
摘要： A function block containing a process-cache tag for storing process-cache tags in the pre-stage of a process cache and an FIFO queue for each tag entry are installed as a traffic controller. The traffic controller stacks packet groups, identified as being from the same flow, in the same FIFO queue. Each FIFO queue records the logged state of the corresponding process queues, and when a packet arrives at an FIFO queue entry in a non-registered state, only its first packet is conveyed to a function block for processing the process-cache misses, and then it awaits registration in a process cache. Access to the process cache from the FIFO queue is implemented at the time that registration of the second and subsequent packets in the process cache are completed. This allows packets other than the first packet in the flow to always access the process cache for a cache hit.
摘要翻译：包含用于在过程高速缓存的前级中存储过程高速缓存标签的过程高速缓存标签和用于每个标签条目的FIFO队列的功能块被安装为流量控制器。流量控制器在相同的FIFO队列中堆叠被标识为来自相同流的分组组。每个FIFO队列记录相应进程队列的记录状态，当一个数据包到达非注册状态的FIFO队列条目时，只将其第一个数据包传送到一个功能块，以处理进程高速缓存未命中，然后它等待进程缓存中的注册。在过程高速缓存中的第二个和后续数据包的注册完成时实现从FIFO队列访问进程缓存。这允许流中的第一个数据包以外的数据包始终访问缓存命中的进程缓存。

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