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11. 发明授权

US06399959B1 Thin film transistor with reduced metal impurities 失效
标题翻译：具有减少金属杂质的薄膜晶体管
公开(公告)号：US06399959B1
公开(公告)日：2002-06-04
申请号：US09799048
申请日：2001-03-06
申请人： Ting-Chang Chang , Ching-Wei Chen
发明人： Ting-Chang Chang , Ching-Wei Chen
IPC分类号： H01L2904
CPC分类号： H01L29/66757 , H01L29/78603 , H01L29/78609 , H01L29/78675
摘要： A structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.
摘要翻译：用于形成具有减少的金属杂质的薄膜晶体管的结构。该结构至少包括以下步骤。首先是绝缘基板。然后，绝缘基板上的绝缘吸气层，其中非晶硅层限定有源区，绝缘吸气层上的沟道区，与沟道区相邻的绝缘吸气层上的源极区，与沟道区相邻并且与源极区相反的绝缘吸杂层和沟道区上的栅极，其中源极，漏极，绝缘吸杂层和沟道区是晶体管的部件。

12. 发明授权

US06232198B1 Method for fabricating electrode 失效
标题翻译：电极制造方法
公开(公告)号：US06232198B1
公开(公告)日：2001-05-15
申请号：US09321510
申请日：1999-05-27
申请人： Ting-Chang Chang , Po-Tsun Liu
发明人： Ting-Chang Chang , Po-Tsun Liu
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/288 , H01L28/55
摘要： A method for fabricating a noble metal electrode of a capacitor. A substrate having a doped region is provided. A dielectric layer is formed to cover the substrate including the doped region with a contact is penetrating through the dielectric layer to couple with the doped region. A barrier layer is formed to cover the dielectric layer and the contact. A polysilicon layer is formed on the barrier layer. The polysilicon layer and TiN barrier layer are etched to form an electrode pattern. The chip is immersed in a solution having noble metal ions and reducing agent for the noble metal ions. In such solution, a displacement reaction takes place to displace the polysilicon layer by a noble metal layer. After the immersion step, the chip is annealed to densify the noble metal layer.
摘要翻译：一种用于制造电容器的贵金属电极的方法。提供具有掺杂区域的衬底。形成介电层以覆盖包括掺杂区域的衬底，其中触点穿过介电层以与掺杂区域耦合。形成阻挡层以覆盖介电层和接触。在阻挡层上形成多晶硅层。蚀刻多晶硅层和TiN阻挡层以形成电极图案。将该芯片浸入具有贵金属离子和贵金属离子还原剂的溶液中。在这种解决方案中，发生置换反应以通过贵金属层移置多晶硅层。在浸渍步骤之后，将芯片退火以使贵金属层致密。

13. 发明授权

US6156671A Method for improving characteristic of dielectric material 有权
标题翻译：改善介电材料特性的方法
公开(公告)号：US6156671A
公开(公告)日：2000-12-05
申请号：US266177
申请日：1999-03-10
申请人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
发明人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/31
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/0234 , H01L21/3122 , H01L21/31058
摘要： A method for improving a characteristic of a dielectric material. A methylsilsesquioxane having a low dielectric constant is used as a dielectric material. A methylsilsesquioxane film is formed on a substrate. A baking process is performed on the methylsilsesquioxane film, and then a curing process is performed on the methylsilsesquioxane film. Next, a hydrogen plasma treatment is performed on the surface of the methylsilsesquioxane film to prevent the methylsilsesquioxane film from being damaged by oxygen plasma for removing photoresist layer, so that the characteristically low dielectric constant of the methylsilsesquioxane film is maintained.
摘要翻译：一种改善介电材料特性的方法。使用具有低介电常数的甲基倍半硅氧烷作为介电材料。在基板上形成甲基倍半硅氧烷膜。对甲基倍半硅氧烷膜进行烘烤处理，然后对甲基倍半硅氧烷膜进行固化处理。接着，对甲基倍半硅氧烷膜的表面进行氢等离子体处理，以防止甲基倍半硅氧烷膜被除去光致抗蚀剂层的氧等离子体损坏，从而维持甲基硅倍半氧烷薄膜的特性低的介电常数。

14. 发明授权

US6004836A Method for fabricating a film transistor 失效
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US6004836A
公开(公告)日：1999-12-21
申请号：US238110
申请日：1999-01-27
申请人： Ting-Chang Chang , Jing-Woei Chen , Po-Sheng Shih
发明人： Ting-Chang Chang , Jing-Woei Chen , Po-Sheng Shih
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66757 , H01L29/7866 , H01L29/78666 , H01L29/78675
摘要： A method to form a TFT includes providing an insulating substrate. An amorphous silicon layer, a first polysilicon layer, an oxide layer, a second polysilicon layer are sequentially formed on the insulating substrate and are patterned to form an active region. On the active region, there are a desired gate region, and a desired interchangeable source/drain region. A portion of the second polysilicon, the oxide layer, the first polysilicon layer above the desired interchangeable source/drain region are removed, and a top portion of the amorphous-Si layer with a depth is also removed. The remaining portion of the a-Si layer is converted into a conductive layer through, for example, laser crystallization method so as to serve as the interchangeable source/drain region.
摘要翻译：形成TFT的方法包括提供绝缘基板。在绝缘基板上依次形成非晶硅层，第一多晶硅层，氧化物层，第二多晶硅层，并对其进行构图以形成有源区。在有源区域上，存在所需的栅极区域和期望的可互换的源极/漏极区域。去除部分第二多晶硅，氧化物层，期望的可互换源极/漏极区域上方的第一多晶硅层，并且除去具有深度的非晶硅层的顶部。通过例如激光结晶法将a-Si层的剩余部分转换成导电层，以作为可互换的源极/漏极区域。

15. 发明申请

US20130234094A1 Methods and Apparatus for Resistive Random Access Memory (RRAM) 有权
标题翻译：电阻随机存取存储器（RRAM）的方法和装置
公开(公告)号：US20130234094A1
公开(公告)日：2013-09-12
申请号：US13416183
申请日：2012-03-09
申请人： Ting-Chang Chang , Yong-En Syu , Fu-Yen Jian , Shih-Chieh Chang , Ying-Lang Wang
发明人： Ting-Chang Chang , Yong-En Syu , Fu-Yen Jian , Shih-Chieh Chang , Ying-Lang Wang
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/12 , H01L45/145 , H01L45/1608
摘要： Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
摘要翻译：公开了一种用于电阻随机存取存储器（RRAM）装置的方法和装置。 RRAM器件包括底电极，设置在底电极上的电阻开关层和设置在电阻开关层上的顶电极。电阻开关层由金属，Si和O的复合材料制成。在顶部电极和底部电极之间可能存在额外的隧道势垒层。顶部电极和底部电极可以包括多个子层。

16. 发明授权

US07813142B2 Portable electronic device with conducting pole 有权
标题翻译：带导电杆的便携式电子设备
公开(公告)号：US07813142B2
公开(公告)日：2010-10-12
申请号：US11952973
申请日：2007-12-07
申请人： Kuan-Chang Lin , Ting-Chang Chang
发明人： Kuan-Chang Lin , Ting-Chang Chang
IPC分类号： H01R9/00
CPC分类号： H01R13/2421 , H01R12/714 , H05K1/0215 , H05K2201/10318 , H05K2203/176
摘要： A portable electronic device (20) includes a circuit board (21) and at least one conducting pole (22). The conducting pole is mounted on the circuit board and includes a breakable portion (2224), the breakable portion is configured to be the part that breaks when the conducting pole is crumpled.
摘要翻译：便携式电子设备（20）包括电路板（21）和至少一个导电极（22）。所述导电极安装在所述电路板上，并且包括可破坏部分（2224），所述可破坏部分被构造为当所述导电柱被弄皱时所述部件断裂。

17. 发明授权

US06673661B1 Self-aligned method for forming dual gate thin film transistor (TFT) device 有权
标题翻译：用于形成双栅极薄膜晶体管（TFT）器件的自对准方法
公开(公告)号：US06673661B1
公开(公告)日：2004-01-06
申请号：US10324965
申请日：2002-12-20
申请人： Chi-Wen Liu , Ting-Chang Chang , Po-Tsun Liu , Ying-Lang Wang
发明人： Chi-Wen Liu , Ting-Chang Chang , Po-Tsun Liu , Ying-Lang Wang
IPC分类号： H01L2184
CPC分类号： H01L29/6675 , H01L29/78612 , H01L29/78618 , H01L29/78648 , H01L29/78684
摘要： A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.
摘要翻译：制造双栅极薄膜晶体管（TFT）器件的方法提供了形成相对于第一栅极电极自对准的一对源极/漏极层，并且形成相对于所述一对栅极电极自对准的第二栅电极源极/漏极层和第一栅极电极。因此，双栅极TFT器件被制造成具有增强的对准。此外，双栅极TFT器件（或单栅极TFT器件）可以由硅 - 锗合金材料形成的源极/漏极层制造，以提供相对于扭结效应具有增强性能的TFT器件。

18. 发明授权

US06521547B1 Method of repairing a low dielectric constant material layer 有权
标题翻译：修复低介电常数材料层的方法
公开(公告)号：US06521547B1
公开(公告)日：2003-02-18
申请号：US09682479
申请日：2001-09-07
申请人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L2131
CPC分类号： H01L21/3105 , H01L21/31058 , H01L21/31138 , H01L21/76802
摘要： A method of repairing a low dielectric constant (low k) material layer starts with coating a photoresist layer on the low k material layer on a semiconductor wafer. After transferring a pattern of the photoresist layer to the low k material layer, an oxygen plasma ashing process is performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed so as to repair damage to the low k material layer caused by the oxygen plasma ashing process, and to enhance a surface of the low k material layer to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.
摘要翻译：修复低介电常数（低k）材料层的方法首先在半导体晶片上的低k材料层上涂覆光致抗蚀剂层。在将光致抗蚀剂层的图案转印到低k材料层之后，进行氧等离子体灰化处理以除去光致抗蚀剂层。最后，通过使低k材料层与包含烷基和卤素取代基的烷基硅烷的溶液接触，除去在氧等离子体灰化过程中在低k层中形成的Si-OH键，以修复对低k 由氧等离子体灰化过程引起的材料层，并且将低k材料层的表面增强到疏水表面以防止水分粘附到低k材料层的表面。

19. 发明授权

US06486496B2 Polysilicon thin film transistor structure 有权
标题翻译：多晶硅薄膜晶体管结构
公开(公告)号：US06486496B2
公开(公告)日：2002-11-26
申请号：US09994322
申请日：2001-11-26
申请人： Ting-Chang Chang , Hsiao-Wen Zan , Po-Sheng Shih
发明人： Ting-Chang Chang , Hsiao-Wen Zan , Po-Sheng Shih
IPC分类号： H01L21108
CPC分类号： H01L29/66757 , H01L29/78621 , H01L29/78627 , H01L29/78666 , H01L29/78684
摘要： A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.
摘要翻译：一种形成多晶硅薄膜晶体管的方法。在绝缘基板上形成非晶硅沟道层。在非晶硅沟道层中形成有源区。在非晶硅沟道层上依次形成氧化物层和栅电极。在非晶硅沟道层中形成轻掺杂的源极/漏极区，然后在栅极上形成间隔物。源极/漏极区域形成在非晶硅沟道层中。除去源极/漏极区上方的氧化物层的一部分。在间隔物的侧壁上形成隔离间隔物。在间隔物的顶部和源极/漏极区域上形成自对准的硅化物层。最后，进行金属诱导的横向结晶工艺以将非晶硅沟道层转变成横向结晶 - 多晶硅沟道层。

20. 发明授权

US06171717B2 Structure of stacked barrier layer 有权
标题翻译：层叠阻挡层的结构
公开(公告)号：US06171717B2
公开(公告)日：2001-01-09
申请号：US09181303
申请日：1998-10-28
申请人： Ting-Chang Chang , Jung-Chih Hu
发明人： Ting-Chang Chang , Jung-Chih Hu
IPC分类号： B32B1800
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76846
摘要： A structure of a stacked barrier layer is provided. A first titanium layer is formed on a semiconductor substrate using plasma enhanced chemical vapor deposition (PECVD). At least a stacked barrier layer is formed on the first titanium layer. The stacked barrier layer includes a first titanium nitride layer and a plasma treated titanium nitride layer. The plasma treated titanium nitride layer is treated using a plasma gas including ammonia gas and nitrogen gas.
摘要翻译：提供层叠阻挡层的结构。使用等离子体增强化学气相沉积（PECVD）在半导体衬底上形成第一钛层。至少在第一钛层上形成层叠的阻挡层。堆叠的阻挡层包括第一氮化钛层和等离子体处理的氮化钛层。使用包括氨气和氮气的等离子体气体处理等离子体处理的氮化钛层。

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