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    • 11. 发明授权
    • Compositing images from multiple sources
    • 从多个来源组合图像
    • US07602406B2
    • 2009-10-13
    • US10968703
    • 2004-10-19
    • Donald M. Gray, IIIJohn Allen Tardif
    • Donald M. Gray, IIIJohn Allen Tardif
    • G09G5/00
    • G09G5/14G06F3/14G09G2340/10G09G2340/125G09G2370/04
    • Systems and methods for compositing an image directly from multiple source image data for reducing system memory footprint and bandwidth and for improving color quality of the image. The image is divided into spans, lines, and slices. Each line includes at least one span and each slice includes at least one line. All lines in a slice have spans associated with identical sources. An image is composited by reading the image data directly from one or more sources of each span. If necessary, the sources are blended. A control structure is used to provide the image context and identifies the sources of the spans. The control structure includes headers for each data stream from each source of each span. Also, the color quality of the image is improved by reducing the number of color space conversions that occur as the image is composited. All sources in the same color space are blended before being blended with sources from other color spaces. Preferably, no more than a single color conversion is required.
    • 用于从多个源图像数据直接合成图像的系统和方法,以减少系统内存占用和带宽,并提高图像的色彩质量。 图像分为跨度,线和切片。 每行包括至少一个跨度,每个切片包括至少一个直线。 切片中的所有行都具有与相同源相关联的跨度。 通过直接从每个跨度的一个或多个来源读取图像数据来合成图像。 如果需要,混合来源。 控制结构用于提供图像上下文并识别跨度的来源。 控制结构包括来自每个跨度的每个源的每个数据流的头部。 此外,通过减少图像合成时发生的色彩空间转换次数,可以提高图像的色彩质量。 在与其他颜色空间的源混合之前,将相同颜色空间中的所有来源混合。 优选地,不需要单独的颜色转换。
    • 13. 发明授权
    • Verification of server authorization to provide network resources
    • 验证服务器授权提供网络资源
    • US06910136B1
    • 2005-06-21
    • US09978536
    • 2001-10-16
    • Steven C. WassermanToby E. FarrandDonald M. Gray, III
    • Steven C. WassermanToby E. FarrandDonald M. Gray, III
    • H04L29/06G06F11/30G06F12/14H04L9/00H04L9/32
    • H04L63/0869H04L63/0478H04L67/42
    • Systems and methods for verifying the authorization of a server to provide network resources to a client. At selected times, the client asserts an authorization interrupt, which will disable some or all non-essential functions of the client unless the server's authorization is verified within an allotted period of time. The client creates a client message by generating a random number and combining it with a client identifier and a value that specifies the current time. The client message is encrypted and sent to the server. Only authorized servers can decrypt the client message and create an encrypted service message that includes the random number. The service message can also contain an authorization code specifying the services that the client may receive, and an expiration count indicating when the authorization procedure will be repeated. The client receives and decrypts the service message. If the random number in the service message is found to be the same as the random number in the client message, the server is authorized, and the client is enabled to exhibit a selected level of functionality. The client can be associated with a smart card or another intelligent peripheral that verifies the authorization of the server in behalf of the client.
    • 用于验证服务器向客户端提供网络资源的授权的系统和方法。 在选定的时间,客户断言授权中断,这将禁用客户端的一些或所有非基本功能,除非在分配的时间段内验证服务器的授权。 客户端通过生成随机数创建客户端消息,并将其与客户端标识符和指定当前时间的值组合。 客户端消息被加密并发送到服务器。 只有授权的服务器可以解密客户端消息,并创建包含随机数的加密服务消息。 服务消息还可以包含指定客户端可以接收的服务的授权码,以及指示何时将重复授权过程的到期计数。 客户端接收并解密服务消息。 如果发现服务消息中的随机数与客户端消息中的随机数相同,则授权服务器,并且允许客户端呈现所选择的功能级别。 客户端可以与智能卡或另一个智能外设相关联,以便代表客户端验证服务器的授权。
    • 14. 发明授权
    • Digital signal processor architecture
    • 数字信号处理器架构
    • US5752073A
    • 1998-05-12
    • US501163
    • 1995-07-11
    • Donald M. Gray, IIIDavid L. Needle
    • Donald M. Gray, IIIDavid L. Needle
    • G06F9/30G06F9/302G06F9/32G06F9/38G06F9/00
    • G06F9/3001G06F9/30094G06F9/30134G06F9/30145G06F9/30167G06F9/322G06F9/3824G06F9/3867
    • A digital signal processing architecture is inherently cyclical in nature, by providing a timer which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input sample stream. Pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers. The processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO. Similarly, whenever the processor writes data to one of the locations corresponding to an output FIFO, control means automatically recognizes that and copies the data into the corresponding output FIFO. Output FIFO writes may be emulated by an address latch and a data latch in a path to the FIFOs. The processor also includes instructions with a "write-back" bit, a novel register addressing mode, a "branch from" instruction, an invisible move function, and an operand mask register.
    • 数字信号处理架构本质上是周期性的,通过提供定时器,其可以被编程以重置处理器并且周期性地返回到第一指令,通常一次输入样本流的每个采样。 通过使用双缓冲系统来增强管道操作,其中操作数一旦被准备就被锁存在双缓冲器的第一级中,但是只有当最后一个就绪操作数可用时它们被传送到第二级, 计算单元准备好接收操作数。 计算单元接收缓冲器的第二级中的操作数。 处理器通过随机存取存储器和多个FIFO与外部单元进行通信。 每个FIFO与随机存取存储器中的相应位置相关联。 每当处理器从随机存取存储器中的这些位置中的一个获取值时,控制装置自动将该位置从相应的FIFO重新填充。 类似地,只要处理器将数据写入对应于输出FIFO的位置之一,控制装置自动识别并将数据复制到相应的输出FIFO中。 输出FIFO写操作可以通过FIFO中的地址锁存器和数据锁存器进行仿真。 该处理器还包括具有“回写”位,新型寄存器寻址模式,“分支从”指令,不可见移动功能和操作数掩码寄存器的指令。
    • 15. 发明授权
    • Arbitrating and servicing polychronous data requests in direct memory access
    • 在直接内存访问中仲裁和服务多同步数据请求
    • US07389365B2
    • 2008-06-17
    • US11126111
    • 2005-05-10
    • Donald M. Gray, IIIAgha Zaigham Ahsan
    • Donald M. Gray, IIIAgha Zaigham Ahsan
    • G06F13/28
    • G06F13/28
    • Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.
    • 用于维护系统设备的数据和内存要求的系统。 提供了包括数据存储器的DMA引擎,其管理和仲裁来自系统设备的数据请求。 提供了一个仲裁单元,只允许符合条件的设备在任何给定的周期内进行数据请求,以确保所有设备在可编程时间段内被服务。 数据储存器包含每个设备的每个通道的数据缓冲区。 存储器接口通过基于每个通道的分析向数据存储器发出请求来确保数据存储器中存在足够的数据。 基于此分析,可以向系统的主存储器发出请求,否则通道将等待再次进行评估。 从而保证每个通道的响应时间。