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11. 发明授权

US06141350A Auto-negotiation using negative link pulses 有权
标题翻译：使用负链路脉冲进行自动协商
公开(公告)号：US06141350A
公开(公告)日：2000-10-31
申请号：US291036
申请日：1999-04-14
申请人： Dinesh Mahale , Thomas J. Runaldue
发明人： Dinesh Mahale , Thomas J. Runaldue
IPC分类号： H04J3/06 , H04L5/14 , H04L12/24 , H04L12/413 , H04L25/03 , H04L29/06 , H04L29/08 , H04L12/40 , H04J3/02
CPC分类号： H04L25/03885 , H04J3/0688 , H04L12/40032 , H04L12/413 , H04L41/046 , H04L5/1438 , H04L69/323 , H04L49/3054
摘要： A novel auto-negotiation system capable of performing auto-negotiation using negative link pulses. The auto-negotiation system operates in a network transceiver for interconnecting multiple hub communication devices having different operating speeds and link partners provided on a transmission medium. The network transceiver comprises physical layer devices for supporting data exchange between the hub devices and the link partners, and an auto-negotiation device that transmits and receives link pulses of a prescribed polarity carrying auto-negotiation information to and from the link partners to select a mode of communication between the hub devices and the link partners. A reverse polarity detection and correction circuit is provided for supporting auto-negotiation operations when link pulses received from a link partner have a reverse polarity. In a preferred embodiment, the reverse polarity detection and correction circuit comprises a polarity detector for detecting polarity of the link pulses received from the link partner, and a link pulse detector for distinguishing link pulses from data received from the link partner. A polarity reversing circuit responsive to the polarity detector and the link pulse detector reverses polarity of the received link pulses.
摘要翻译：一种能够使用负链路脉冲执行自动协商的新型自动协商系统。自动协商系统在网络收发器中操作，用于互连具有不同操作速度的多个集线器通信设备和设置在传输介质上的链路伙伴。网络收发器包括用于支持集线器设备和链路伙伴之间的数据交换的物理层设备，以及自动协商设备，该设备向链路伙伴发送和接收带有自动协商信息的规定极性的链路脉冲，以选择一个集线器设备和链路伙伴之间的通信模式。提供了反向极性检测和校正电路，用于在从链路伙伴接收到的链路脉冲具有相反极性时支持自动协商操作。在优选实施例中，反极性检测和校正电路包括用于检测从链路伙伴接收的链路脉冲的极性的极性检测器和用于区分链路脉冲与从链路伙伴接收的数据的链路脉冲检测器。响应于极性检测器和链路脉冲检测器的极性反转电路反转所接收的链路脉冲的极性。

12. 发明授权

US6115389A Auto-negotiation for multiple ports using shared logic 失效
标题翻译：使用共享逻辑自动协商多个端口
公开(公告)号：US6115389A
公开(公告)日：2000-09-05
申请号：US291030
申请日：1999-04-14
申请人： Dinesh Mahale , Thomas J. Runaldue
发明人： Dinesh Mahale , Thomas J. Runaldue
IPC分类号： G01B7/02 , G01R31/08 , H04B3/46 , H04J3/06 , H04L5/14 , H04L12/24 , H04L12/413 , H04L12/46 , H04L25/03 , H04L29/06 , H04L29/08 , H04B7/212 , H04L12/43
CPC分类号： H04L25/03885 , G01B7/02 , H04B3/46 , H04J3/0688 , H04L12/40032 , H04L12/413 , H04L12/4625 , H04L41/046 , H04L5/1438 , H04L69/18 , H04L69/323 , G01R31/086 , H04L49/3054
摘要： A data communication device having multiple ports is provided with an auto-negotiation system for performing auto-negotiation with multiple link partners connected to the ports. The auto-negotiation system has a memory and an auto-negotiation unit including transmit, receive and arbitration state machines for performing transmit, receive and arbitration state diagrams compliant with the IEEE 802.3 Standard. The auto-negotiation unit operates in a time-division multiplexing mode using successive time slots for supporting auto-negotiation operations for different ports. The memory is used for storing state diagram variables for a port in a time interval between the time slots assigned to that port.
摘要翻译：具有多个端口的数据通信设备设置有用于与连接到端口的多个链路伙伴进行自动协商的自动协商系统。自动协商系统具有存储器和自动协商单元，包括用于执行符合IEEE 802.3标准的发送，接收和仲裁状态图的发送，接收和仲裁状态机。自动协商单元使用连续时隙以时分多路复用方式工作，以支持不同端口的自动协商操作。内存用于在分配给该端口的时隙之间的时间间隔内存储端口的状态图变量。

13. 发明授权

US6084878A External rules checker interface 失效
标题翻译：外部规则检查器界面
公开(公告)号：US6084878A
公开(公告)日：2000-07-04
申请号：US993715
申请日：1997-12-18
申请人： Ian Crayford , Denise Kerstein , Peter Ka-Fai Chow , Chandan Egbert , Thomas J. Runaldue
发明人： Ian Crayford , Denise Kerstein , Peter Ka-Fai Chow , Chandan Egbert , Thomas J. Runaldue
IPC分类号： H04L12/46 , H04L12/56 , H04L12/28 , H04L12/54
CPC分类号： H04L12/4641 , H04L49/25 , H04L49/3027 , H04L49/351 , H04L49/354
摘要： An interface located on a network switch transmits header information to an external device that makes data forwarding decisions. The interface receives and transmits header information that includes the source and destination address of the data. The external device generates data forwarding information and transmits the information back to the switch via the interface device. The network switch uses the information obtained via the interface and forwards the data packets to the appropriate destination.
摘要翻译：位于网络交换机上的接口将报头信息发送到进行数据转发决策的外部设备。该接口接收并发送包括数据的源地址和目标地址的标题信息。外部设备生成数据转发信息，并通过接口设备将信息发送回交换机。网络交换机使用通过接口获得的信息，并将数据包转发到适当的目的地。

14. 发明授权

US5835719A Apparatus and method for remote wake-up in system having interlinked networks 失效
标题翻译：具有互连网络的系统中用于远程唤醒的装置和方法
公开(公告)号：US5835719A
公开(公告)日：1998-11-10
申请号：US972093
申请日：1997-11-17
申请人： Glen Gibson , Thomas J. Runaldue , Ching Yu
发明人： Glen Gibson , Thomas J. Runaldue , Ching Yu
IPC分类号： G06F1/32 , H04L12/12 , G06F13/38
CPC分类号： G06F1/3209 , H04L12/12 , Y02B60/32 , Y02B60/34
摘要： An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.
摘要翻译：公开了一种用于在具有互连网络（例如，路由器互连LAN）的数据交换系统内远程唤醒预期节点的装置和方法。公开了一种唤醒命令格式，其中对应于预期节点的地址的序列通过从远程源节点发送的一个或多个分组的相应数据字段被广泛地连续N次（例如，至少16个连续时间）到目标节点。当预期节点处于睡眠模式时，当预定节点接收到该特定序列时，响应地启动唤醒操作，使得休眠节点至少在一段时间内唤醒以响应未来接收到的分组。

15. 发明授权

US06393021B1 Integrated multiport switch having shared data receive FIFO structure 失效
标题翻译：具有共享数据接收FIFO结构的集成多端口开关
公开(公告)号：US06393021B1
公开(公告)日：2002-05-21
申请号：US08992815
申请日：1997-12-18
申请人： Peter Ka-Fai Chow , Thomas J. Runaldue
发明人： Peter Ka-Fai Chow , Thomas J. Runaldue
IPC分类号： H04Q1100
CPC分类号： H04L49/3009 , G06F13/1605 , G06F13/24 , G11C11/412 , H04L12/1863 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L41/0213 , H04L47/50 , H04L47/6225 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/255 , H04L49/30 , H04L49/3027 , H04L49/3054 , H04L49/351 , H04L49/354 , H04L49/40 , H04L49/50 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9063 , H04L49/9073 , H04L49/9078 , H04L49/9084 , H04Q3/54591 , H04Q2213/1316 , H04Q2213/13162
摘要： An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM. When the accumulated data for a given port is to be written to the RAM in a subsequent write cycle, it is then combined with additional incoming data for the same port received at that time for transfer to the RAM.
摘要翻译：具有具有单端口RAM的接收FIFO结构的集成多端口交换机（IMS），用于存储从交换机的每个端口接收的网络通信数据。 RAM连接到FIFO控制单元，FIFO控制单元通过FIFO存储器输入总线通过MAC总线与每个端口的MAC耦合。通过MAC总线将从每个端口接收到的数据写入RAM是以时间共享为基础进行控制的。 FIFO控制单元包括接收RAM接口，该接口连接到MAC总线，用于接收来自端口的通信数据和FIFO存储器输入总线，用于将通信数据传送到RAM用于临时存储。由于FIFO存储器输入总线具有比MAC总线更大的位传输容量，所以接收RAM接口可以在从单端口RAM读取数据的时钟周期期间累加输入数据。当给定端口的累加数据在随后的写周期中被写入RAM时，然后将其与用于传送到RAM的同一端口的附加输入数据组合。

16. 发明授权

US5672993A CMOS current mirror 失效
标题翻译： CMOS电流镜
公开(公告)号：US5672993A
公开(公告)日：1997-09-30
申请号：US601898
申请日：1996-02-15
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G05F3/26 , H03K17/62
CPC分类号： G05F3/262
摘要： A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32,MP33), a variable input current source (I.sub.CS), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit 212. The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).
摘要翻译：用于在CMOS集成电路技术中镜像电流的电流镜电路包括由第一和第二P沟道MOS晶体管（MP32，MP33），可变输入电流源（ICS），第一源极跟随器晶体管（MN34），第二源极跟随器晶体管（MP35），电流吸收晶体管（MN31）和负载电路212.负载电路由负载晶体管（MN36）和负载电阻（R1）构成。在替代实施例中，负载电路由单个负载电阻器形成。结果，注入第一P沟道MOS晶体管（MP32）的电流量更精确地镜像到第二P沟道MOS晶体管（MP33）中。

17. 发明授权

US5191244A N-channel pull-up transistor with reduced body effect 失效
标题翻译：具有减少身体效应的N沟道拉杆晶体管
公开(公告)号：US5191244A
公开(公告)日：1993-03-02
申请号：US760313
申请日：1991-09-16
申请人： Thomas J. Runaldue , Qazi R. M. Mahmood
发明人： Thomas J. Runaldue , Qazi R. M. Mahmood
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H03K17/041 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0952
CPC分类号： H03K17/04106 , H01L27/088 , H03K17/162 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transitor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).
摘要翻译：采用具有减小的体效应的N沟道上拉晶体管的CMOS输出缓冲电路包括N沟道上拉晶体管（N2），N沟道耦合晶体管（N1）和N沟道放电晶体管（N3 ）。上拉晶体管的漏极连接到上电源电位（VCC），其源极连接到输出节点（20），其栅极连接到第一内部节点（B），并且其栅极连接到第二内部节点内部节点（A）。耦合晶体管的源极连接到第二内部节点（A），其漏极连接到上拉晶体管的源极，其栅极连接到第一内部节点（B），其局部衬底连接到局部衬底的上拉电阻（N2）。放电晶体管的漏极连接到第二内部节点（A），其源极连接到较低的电源电位（VCC），其栅极连接到第三个内部节点（C），其局部衬底连接到较低功率电源（VSS）。耦合晶体管和放电晶体管用于减小上拉晶体管（N2）的体效应，并提供较高的上电源电压（VCC）上的噪声抗扰度。

18. 发明授权

US5027008A CMOS clamp circuits 失效
标题翻译： CMOS钳位电路
公开(公告)号：US5027008A
公开(公告)日：1991-06-25
申请号：US480400
申请日：1990-02-15
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： H03K5/007 , H03K5/08 , H03K19/00 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/0016 , H03K19/018521 , H03K5/08
摘要： A CMOS clamp circuit includes a sense inverter (I5) having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor (N5), and a P-channel MOS clamping transistor (P5). The N-channel clamping transistor (N5) has its drain connected to an upper power supply potential (VCC) and its source connected to the input node of the inverter (I5). The P-channel clamping transistor (P5) has its drain connected to a lower power supply potential (VSS) and its source connected to the input node of the sense inverter (I5). The gates of the N-channel and P-channel transistors (N5, P5) are connected to the output node of the sense inverter (I5). An enabling transistor and a power-down transistor may also be provided so as to operate the clamp circuit in a power-down mode of operation.

19. 发明授权

US6058112A Internal rules checker diagnostic mode 失效
标题翻译：内部规则检查器诊断模式
公开(公告)号：US6058112A
公开(公告)日：2000-05-02
申请号：US992492
申请日：1997-12-18
申请人： Denise Kerstein , Thomas J. Runaldue
发明人： Denise Kerstein , Thomas J. Runaldue
IPC分类号： H04L13/08 , G06F11/26 , G06F12/00 , G06F13/00 , G06F13/10 , G06F13/16 , G06F13/24 , G06F15/00 , G06F15/16 , G08B5/00 , G11C11/412 , H04B7/14 , H04J3/02 , H04J3/12 , H04J3/22 , H04J3/24 , H04L12/18 , H04L12/24 , H04L12/28 , H04L12/413 , H04L12/44 , H04L12/46 , H04L12/50 , H04L12/54 , H04L12/66 , H04L12/861 , H04L12/863 , H04L12/879 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/939 , H04L12/947 , H04Q3/545 , H04Q11/00
CPC分类号： H04L49/3009 , G06F13/1605 , G06F13/24 , G11C11/412 , H04L12/4641 , H04L12/5693 , H04L41/0213 , H04L47/6225 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/255 , H04L49/30 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/50 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9063 , H04L49/9073 , H04L49/9078 , H04L49/9084 , H04Q3/54591 , H04L12/1863 , H04L12/4645 , H04L12/467 , H04L49/3054 , H04L49/40 , H04Q2213/1316 , H04Q2213/13162
摘要： A network switch data decision making engine is diagnosed while the switch is operating or after an error is detected. The switch receives data from connected stations and sends header information to the decision making engine. The header information is simultaneously transmitted to an external device. The decision making engine generates a data forwarding decision and outputs the decision to the external device. The operation of the decision making engine can then be checked by an external crevice, such as a logic analyzer.
摘要翻译：网络交换机数据决策引擎在交换机正在运行或检测到错误后被诊断。交换机从连接的站接收数据，并将头信息发送给决策引擎。标题信息同时发送到外部设备。决策引擎生成数据转发决策，并将决定输出到外部设备。决策引擎的操作可以由诸如逻辑分析仪之类的外部缝隙来检查。

20. 发明授权

US5576560A Dual port memory, such as used in color lookup tables for video systems 失效
标题翻译：双端口存储器，例如用于视频系统的颜色查找表
公开(公告)号：US5576560A
公开(公告)日：1996-11-19
申请号：US267036
申请日：1994-06-27
申请人： Thomas J. Runaldue , William Plants
发明人： Thomas J. Runaldue , William Plants
IPC分类号： G09G5/00 , G06T1/20 , G06T1/60 , G09G5/06 , G11C7/10 , H01L21/8244 , H01L27/11 , H01L27/10
CPC分类号： H01L27/1104 , G09G5/06 , G11C7/1075 , Y10S257/903
摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory.Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.A layout configuration of each memory cell and of the memory cell array allows same-channel-type transistors from a plurality of memory cells to be formed in a single, large well, and allows adjacent memory cells to share contacts. This reduces the integrated circuit's size, improves its speed, and increases manufacturing yields.
摘要翻译：一种用于显示系统的颜色查找表的集成电路存储器。存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。视频端口包括隔离的感测端子和两个晶体管。第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。每个存储单元和存储单元阵列的布局配置允许在单个大的阱中形成来自多个存储单元的相同通道型晶体管，并允许相邻的存储单元共享触点。这降低了集成电路的尺寸，提高了其速度，并提高了制造成品率。

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