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11. 发明授权

US07875492B2 Integrated circuit including a memory fabricated using self-aligned processing 有权
标题翻译：集成电路包括使用自对准处理制造的存储器
公开(公告)号：US07875492B2
公开(公告)日：2011-01-25
申请号：US12020988
申请日：2008-01-28
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
摘要翻译：集成电路包括提供阵列的行和列的晶体管，跨阵列的列中的导电线以及与导电线接触并与导电线自对准的电阻率变化材料元件。集成电路包括与电阻率变化材料元件接触的电极，每个电极与导电线自对准并且耦合到晶体管的源极 - 漏极路径的一侧。

12. 发明申请

US20100032635A1 ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION 失效
标题翻译：低电阻垂直二极管阵列及其生产方法
公开(公告)号：US20100032635A1
公开(公告)日：2010-02-11
申请号：US12188401
申请日：2008-08-08
申请人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： H01L47/00 , H01L29/66 , H01L21/00
CPC分类号： H01L27/24 , Y10S257/91
摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
摘要翻译：描述了包括存储器单元阵列和相应的制造方法的集成电路。每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

13. 发明授权

US07495946B2 Phase change memory fabricated using self-aligned processing 失效
标题翻译：使用自对准处理制造的相变存储器
公开(公告)号：US07495946B2
公开(公告)日：2009-02-24
申请号：US11366706
申请日：2006-03-02
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.
摘要翻译：存储器包括行和列中的晶体管，其在阵列中的列中提供阵列和导线。存储器包括与导线接触并与导线自对准的相变元件。每个相变元件耦合到晶体管的源 - 漏路径的一侧。

14. 发明申请

US20070103971A1 Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device 有权
标题翻译：具有多个存储器单元的存储器件，特别是PCM存储器单元，以及用于操作这种存储器单元器件的方法
公开(公告)号：US20070103971A1
公开(公告)日：2007-05-10
申请号：US11269898
申请日：2005-11-09
申请人： Ulrike Gruening-Von Schwerin , Thomas Happ
发明人： Ulrike Gruening-Von Schwerin , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： The invention relates to a method for operating a memory device, and to a memory device with a plurality of memory cells (1) which each have at least one switching device (13) assigned thereto for controlling, as well as a current supply line and a current discharge line (11, 12), wherein said current supply line (11) and said current discharge line (12) are substantially parallel to each other.
摘要翻译：本发明涉及一种用于操作存储器件的方法，以及一种具有多个存储器单元（1）的存储器件，每个存储器单元分别具有至少一个开关器件（13），用于控制以及电流供应线电流放电线（11,12），其中所述电流线（11）和所述电流放电线（12）基本上彼此平行。

15. 发明授权

US07804708B2 Integrated circuit including an array of memory cells and method 有权
标题翻译：集成电路包括一组存储单元和方法
公开(公告)号：US07804708B2
公开(公告)日：2010-09-28
申请号：US12182698
申请日：2008-07-30
申请人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： G11C11/00 , G11C5/06 , H01L29/02
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
摘要翻译：一种包括存储单元阵列和方法的集成电路。在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

16. 发明授权

US07463507B2 Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device 有权
标题翻译：具有多个存储器单元的存储器件，特别是PCM存储器单元，以及用于操作这种存储器单元器件的方法
公开(公告)号：US07463507B2
公开(公告)日：2008-12-09
申请号：US11269898
申请日：2005-11-09
申请人： Ulrike Gruening-Von Schwerin , Thomas Happ
发明人： Ulrike Gruening-Von Schwerin , Thomas Happ
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： The invention relates to a method for operating a memory device, and to a memory device with a plurality of memory cells (1) which each have at least one switching device (13) assigned thereto for controlling, as well as a current supply line and a current discharge line (11, 12), wherein said current supply line (11) and said current discharge line (12) are substantially parallel to each other.
摘要翻译：本发明涉及一种用于操作存储器件的方法，以及一种具有多个存储器单元（1）的存储器件，每个存储器单元分别具有至少一个开关器件（13），用于控制以及电流供应线电流放电线（11,12），其中所述电流线（11）和所述电流放电线（12）基本上彼此平行。

17. 发明授权

US08742387B2 Resistive memory devices with improved resistive changing elements 有权
标题翻译：具有改进的电阻变化元件的电阻式存储器件
公开(公告)号：US08742387B2
公开(公告)日：2014-06-03
申请号：US12145608
申请日：2008-06-25
申请人： Thomas Happ , Franz Kreupl , Jan Boris Philipp , Petra Majewski
发明人： Thomas Happ , Franz Kreupl , Jan Boris Philipp , Petra Majewski
IPC分类号： H01L47/00 , H01L45/00
CPC分类号： H01L45/1253 , G11C13/0004 , G11C2213/79 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/141 , H01L45/146
摘要： An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
摘要翻译：集成电路包括具有电阻变化存储元件的存储单元。电阻变化存储元件包括第一电极，第二电极和设置在第一和第二电极之间的电阻率变化材料，其中电阻率变化材料被配置为响应于施加电压或电流而改变电阻状态和第二电极。此外，第一电极和第二电极中的至少一个包括绝缘体材料，其包括形成在绝缘体材料内的自组装导电元件。形成在绝缘体材料内的自组装导电元件在将电阻率变化材料切换到不同电阻状态的整个操作期间保持稳定。

18. 发明申请

US20120285512A1 SOLAR CELL ARRAY AND THIN-FILM SOLAR MODULE AND PRODUCTION METHOD THEREFOR 审中-公开
标题翻译：太阳能电池阵列和薄膜太阳能电池组件及其制造方法
公开(公告)号：US20120285512A1
公开(公告)日：2012-11-15
申请号：US13519578
申请日：2011-01-27
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： H01L31/05 , H01L31/18
CPC分类号： H01L31/18 , H01L31/046 , H01L31/0749 , Y02E10/541
摘要： A solar cell array is described which can be designed in particular as a thin-film solar module. A production method for a solar cell array is further described.
摘要翻译：描述了可以特别设计为薄膜太阳能模块的太阳能电池阵列。进一步描述太阳能电池阵列的制造方法。

19. 发明授权

US08250293B2 Data exchange in resistance changing memory for improved endurance 有权
标题翻译：电阻变化记忆中的数据交换，以提高耐力
公开(公告)号：US08250293B2
公开(公告)日：2012-08-21
申请号：US12687951
申请日：2010-01-15
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： G06F12/10 , G06F12/16
CPC分类号： G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0035 , G11C13/0069
摘要： According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.
摘要翻译：根据本发明的一个实施例，提供了一种操作集成电路的方法，该集成电路包括分组成物理存储器单元的多个电阻变化存储器单元。该方法包括：监视分配给物理存储器单元的写入访问号码，每个写入访问号码反映写入访问次数到写入访问号码的物理存储单元; 如果分配给第一物理存储器单元的写访问号码的值超过写访问阈值，则执行数据交换处理，在该数据交换处理期间，存储在第一物理存储单元内的数据内容与第二物理存储单元的数据内容交换物理存储单元具有较低值的写入访问号。

20. 发明授权

US08084799B2 Integrated circuit with memory having a step-like programming characteristic 有权
标题翻译：具有阶梯状编程特性的具有存储器的集成电路
公开(公告)号：US08084799B2
公开(公告)日：2011-12-27
申请号：US11488422
申请日：2006-07-18
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L27/108
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the phase change material form a via or trench memory cell.
摘要翻译：存储单元包括在第一电极和第二电极之间的第一电极，第二电极和相变材料。相变材料具有阶梯状编程特性。第一电极，第二电极和相变材料形成通孔或沟槽存储单元。

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