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11. 发明授权

US5477551A Apparatus and method for optimal error correcting code to parity conversion 失效
标题翻译：用于最优纠错码到奇偶校验转换的装置和方法
公开(公告)号：US5477551A
公开(公告)日：1995-12-19
申请号：US224398
申请日：1994-07-05
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/10
摘要： This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.
摘要翻译：本发明涉及数字计算机中数据整合的一般领域。特别涉及具有奇偶校验系统总线和ECC检查存储器的数字计算机系统。本发明通过将ECC中产生的存储器等待时间减少到奇偶校验转换处理来增加这种系统的性能。

12. 发明授权

US5592684A Store queue including a byte order tracking mechanism for maintaining data coherency 失效
标题翻译：存储队列包括用于维护数据一致性的字节顺序跟踪机制
公开(公告)号：US5592684A
公开(公告)日：1997-01-07
申请号：US279758
申请日：1994-07-22
申请人： Darius D. Gaskins , Terry J. Parks
发明人： Darius D. Gaskins , Terry J. Parks
IPC分类号： G06F13/40 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4059
摘要： A store queue is provided that forms an interface between a primary bus and a secondary bus and which temporarily stores data to be written via a memory or I/O channel to a peripheral device. The store queue allows partial writes executed on the primary bus to be combined within a common word storage cell of an internal FIFO buffer regardless of whether the consecutive partial writes result in an invalid byte combination. If the data being transferred does not constitute an invalid byte combination, the store queue executes a single write cycle on the secondary bus. If the data contained by the word memory cell constitutes an invalid byte combination, the store queue executes two or more partial writes on the secondary bus to transfer the data in the order it was received. The store queue includes a byte order tracking circuit, such as an accumulation counter, for tracking the order in which the bytes are written from the primary bus. The store queue may further include a configuration register that stores a descriptor that identifies certain address regions as order-protected. If the data stored within a particular memory cell of the store queue corresponds to an address within the protective range, the store queue transfers the data on the secondary bus in the same order as it was received from the primary bus.
摘要翻译：提供存储队列，其形成主总线和辅助总线之间的接口，并且将经由存储器或I / O通道写入的数据临时存储到外围设备。存储队列允许在主总线上执行的部分写入被组合在内部FIFO缓冲器的公共字存储单元中，而不管连续的部分写入是否导致无效字节组合。如果正在传输的数据不构成无效字节组合，则存储队列在辅助总线上执行单个写周期。如果字存储器单元包含的数据构成无效字节组合，则存储队列在辅助总线上执行两个或多个部分写入，以按照接收的顺序传送数据。存储队列包括用于跟踪从主总线写入字节的顺序的字节顺序跟踪电路，例如累加计数器。存储队列还可以包括配置寄存器，该配置寄存器存储标识某些地址区域作为订单保护的描述符。如果存储在存储队列的特定存储单元内的数据对应于保护范围内的地址，则存储队列按照从主总线接收的顺序传送辅助总线上的数据。

13. 发明授权

US5463643A Redundant memory channel array configuration with data striping and error correction capabilities 失效
标题翻译：冗余内存通道阵列配置，具有数据分条和纠错能力
公开(公告)号：US5463643A
公开(公告)日：1995-10-31
申请号：US207009
申请日：1994-03-07
申请人： Darius D. Gaskins , Terry J. Parks
发明人： Darius D. Gaskins , Terry J. Parks
IPC分类号： G06F11/10 , G06F11/20 , H03M13/00 , G06F11/00
CPC分类号： G06F11/1008 , G06F11/1048 , G06F11/1076
摘要： A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.
摘要翻译：一种存储器通道阵列配置，其中两个或多个存储器通道用于数据传输，并且数据在每个存储器通道上被条带化。此外，一个或多个冗余存储器通道，优选地是单个专用奇偶校验通道，用于纠错。在优选实施例中，存储器通道配置利用基于RAMBUS的存储器通道，因此本发明为基于RAMBUS的存储器系统提供错误校正。此外，与使用现有技术的RAMBUS技术的实现相比，使用多个存储器通道结合每个通道上的数据条带化允许比数据传输带宽高得多的数据传输带宽。

14. 发明授权

US5261068A Dual path memory retrieval system for an interleaved dynamic RAM memory unit 失效
标题翻译：用于交错动态RAM存储器单元的双路存储器检索系统
公开(公告)号：US5261068A
公开(公告)日：1993-11-09
申请号：US530137
申请日：1990-05-25
申请人： Darius D. Gaskins , Thomas H. Holman, Jr. , Michael L. Longwell , Keith D. Matteson , Terry J. Parks
发明人： Darius D. Gaskins , Thomas H. Holman, Jr. , Michael L. Longwell , Keith D. Matteson , Terry J. Parks
IPC分类号： G06F12/06 , G11C8/12 , G06F12/00 , G11C7/00 , G11C8/00
CPC分类号： G06F12/0607 , G11C8/12
摘要： A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and deasserting an access signal to specified locations of the interleaved memory banks, a multiplexer having a pair of input channels for each memory bank and a pair of data paths from the output of each memory bank to the corresponding input channels of the multiplexer. The first data path is a direct path between the memory bank and a first one of the pair of input channels and the second data path is a latched path between the memory bank and a second one of the pair of input channels.
摘要翻译：一种具有用于由任意数量的交错存储器组成的动态RAM存储器单元的双路存储器检索系统的数字计算机。该系统包括用于断言和解除对交错存储体的指定位置的访问信号的装置，具有用于每个存储体的一对输入通道的多路复用器和从每个存储体的输出到相应输入通道的一对数据路径的多路复用器。第一数据路径是存储体与该对输入通道中的第一数据路径之间的直接路径，而第二数据路径是存储体与该对输入通道中的第二个之间的锁存路径。

15. 发明授权

US5483641A System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities 失效
标题翻译：用于如果新请求在N个最后读取请求之内的附近，则调度可读前置操作的系统，其中N依赖于独立活动
公开(公告)号：US5483641A
公开(公告)日：1996-01-09
申请号：US810277
申请日：1991-12-17
申请人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
发明人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
IPC分类号： G06F3/06 , G06F12/08 , G11B20/18 , G06F13/14
CPC分类号： G06F3/0601 , G06F12/0862 , G11B20/1833 , G11B20/1883 , G06F12/0866 , G06F2003/0697 , G06F2212/6026 , G11B2220/20
摘要： An improved read ahead strategy that improves the performance of a disk array subsystem. The disk controller keeps track of the last n reads to the array. If a new read request is received that is adjacent to any of the last n reads, the controller performs a look ahead read because a sequential read may be in progress. The parameter n is preferably set comparable to or greater than the number of maximum independent activites being performed by the computer system. Therefore, in a multithread system, the controller performs a readahead if any one thread is doing a sequential read.
摘要翻译：改进的预读策略，提高磁盘阵列子系统的性能。磁盘控制器跟踪阵列的最后n次读取。如果接收到与最后n次读取中的任何一个相邻的新的读取请求，则控制器执行预览读取，因为顺序读取可能正在进行中。优选地将参数n设置为等于或大于由计算机系统执行的最大独立运动的数量。因此，在多线程系统中，如果任何一个线程进行顺序读取，则控制器执行readahead。

16. 发明授权

US5473761A Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests 失效
标题翻译：控制器用于接收非连续扇区的传输请求，并通过在传送请求之间散布任何操作请求，将这些扇区读取为连续块
公开(公告)号：US5473761A
公开(公告)日：1995-12-05
申请号：US218866
申请日：1994-03-28
申请人： Terry J. Parks , Kenneth L. Jeffries , Craig S. Jones
发明人： Terry J. Parks , Kenneth L. Jeffries , Craig S. Jones
IPC分类号： G06F3/06 , G06F13/14
CPC分类号： G06F3/0601 , G06F2003/0692
摘要： A disk drive array including a controller which provides scatter/scatter (bi-directional scatter/gather) operations between noncontiguous host memory address locations and noncontiguous disk address locations. The host provides a single request to launch a scatter/scatter transfer. The single data request includes a pointer to a list of transfer counts and addresses, the length of the list, and the starting logical address on the disk transfer. Skipped blocks in a scatter/scatter request are specified by data address value of -1, and a no-operation (no-op) request is enqueued for each skipped block. Thus, during reads the controller extends the scattered read from the disk into a single large read of contiguous sectors and suppresses the unwanted data by inserting "no-operation" commands in place of the read commands during the transfer to the host.
摘要翻译：一种包括控制器的磁盘驱动器阵列，该控制器在不连续的主机存储器地址位置和非连续的磁盘地址位置之间提供散射/散射（双向分散/收集）操作。主机提供单个请求来启动散射/散射传输。单个数据请求包括指向传输计数和地址列表的指针，列表的长度以及磁盘传输的起始逻辑地址。分散/散布请求中的跳过块由数据地址值-1指定，每个跳过块的无操作（无操作）请求都被排入队列。因此，在读取期间，控制器将从盘的分散读取扩展为连续扇区的单个大读取，并且在传送到主机期间通过插入“无操作”命令代替读取命令来抑制不需要的数据。

17. 发明授权

US5619723A System for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activities 失效
标题翻译：用于调度预读操作的系统，如果新请求是最后n个最后读取请求的顺序，其中n在独立活动上不同
公开(公告)号：US5619723A
公开(公告)日：1997-04-08
申请号：US562238
申请日：1995-11-21
申请人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
发明人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
IPC分类号： G06F3/06 , G06F12/08 , G11B20/18 , G06F13/14
CPC分类号： G06F3/0601 , G06F12/0862 , G11B20/1833 , G11B20/1883 , G06F12/0866 , G06F2003/0697 , G06F2212/6026 , G11B2220/20
摘要： A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.
摘要翻译：具有控制器的磁盘驱动器阵列，其提供：用于磁盘驱动器中的长期缺陷的动态重映射，具有可变数量的分叉的多线程请求处理，具有逻辑和物理列表的缺陷跟踪，小于全条带优化的保护写入通过可选择地使用冗余来限制涉及的扇区数量，多个操作与单个磁盘请求的关联以便于错误处理，使用访问间隙作为在后台重建数据的进一步机会的指示以及散射/散射（双向分散/聚合）操作。

18. 发明授权

US5600801A Multiple function interface device for option card 失效
标题翻译：选项卡多功能接口设备
公开(公告)号：US5600801A
公开(公告)日：1997-02-04
申请号：US92044
申请日：1993-07-15
申请人： Terry J. Parks , Craig S. Jones
发明人： Terry J. Parks , Craig S. Jones
IPC分类号： G06F9/445 , G06F6/00
CPC分类号： G06F9/4411
摘要： A device for interfacing an expansion bus with an option card and an associated method for initializing a computer system having the option card installed on the expansion bus thereof. The interface device includes a dual ported RAM having a first port coupled to the expansion bus and a second port coupled to the option card, a processor coupled to the second port of the dual ported RAM and a non-volatile memory coupled to the processor and to the second port of the dual ported RAM. At power up, the processor transfers an expansion BIOS and pattern stored in the non-volatile memory to first and second portions, respectively, of the memory space of the dual ported RAM. The computer system scans the second portion of the dual ported RAM for the pattern, executes a first initialization sequence contained in the expansion BIOS upon detecting the pattern and then executes a second initialization sequence contained in a BIOS of the computer system. Data acquired during the execution of the initialization sequence is stored in a third portion of the memory space. Updates to the expansion BIOS are transferred to a fourth portion of the memory space where the processor transfers the updates to the non-volatile memory. The processor also controls bi-directional exchanges of data and control signals between the expansion bus and the option card via the fourth portion of the memory space.
摘要翻译：用于将扩展总线与选项卡进行接口的装置以及用于初始化具有安装在其扩展总线上的选件卡的计算机系统的相关方法。接口设备包括双端口RAM，其具有耦合到扩展总线的第一端口和耦合到选项卡的第二端口，耦合到双端口RAM的第二端口的处理器和耦合到处理器的非易失性存储器，以及到双端口RAM的第二个端口。在上电时，处理器将存储在非易失性存储器中的扩展BIOS和模式分别转移到双端口RAM的存储器空间的第一和第二部分。计算机系统扫描双端口RAM的第二部分用于模式，在检测到模式时执行包含在扩展BIOS中的第一初始化序列，然后执行包含在计算机系统的BIOS中的第二初始化序列。在执行初始化序列期间获取的数据被存储在存储器空间的第三部分中。扩展BIOS的更新被传送到存储器空间的第四部分，其中处理器将更新传送到非易失性存储器。处理器还通过存储器空间的第四部分来控制扩展总线和选件卡之间的数据和控制信号的双向交换。

19. 发明授权

US5530960A Disk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each other 失效
标题翻译：磁盘驱动器控制器接受访问复合驱动器的第一命令和用于各个诊断驱动器控制的第二命令，其中命令彼此是透明的
公开(公告)号：US5530960A
公开(公告)日：1996-06-25
申请号：US224091
申请日：1994-04-06
申请人： Terry J. Parks , Kenneth L. Jeffries , Craig S. Jones
发明人： Terry J. Parks , Kenneth L. Jeffries , Craig S. Jones
IPC分类号： G06F11/22 , G11B20/18 , G11C29/00 , G06F13/00
CPC分类号： G11C29/74 , G06F11/22 , G11B20/1883 , G11B2220/20
摘要： A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.
摘要翻译：具有控制器的磁盘驱动器阵列，其提供：用于磁盘驱动器中的长期缺陷的动态重映射，具有可变数量的分叉的多线程请求处理，具有逻辑和物理列表的缺陷跟踪，小于全条带优化的保护写入通过可选择地使用冗余来限制涉及的扇区数量，多个操作与单个磁盘请求的关联以便于错误处理，使用访问间隙作为在后台重建数据的进一步机会的指示以及散射/散射（双向分散/聚合）操作。

20. 发明授权

US5452463A Processor and cache controller interface lock jumper 失效
标题翻译：处理器和缓存控制器接口锁定跳线
公开(公告)号：US5452463A
公开(公告)日：1995-09-19
申请号：US119799
申请日：1993-09-10
申请人： Terry J. Parks , Thomas H. Holman, Jr.
发明人： Terry J. Parks , Thomas H. Holman, Jr.
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0888
摘要： A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.
摘要翻译：包括生成计算机系统锁定循环的至少一个处理器和高速缓存子系统的计算机系统包括用于可操作地连接至少一个处理器和高速缓存子系统的跳线组件，以便如果计算机系统包括只有一个处理器，如果计算机系统包含多个处理器，则不可缓存。根据本发明的方法包括以下步骤：确定在计算机系统中是否存在一个或多于一个处理器，然后相应地呈现可锁定循环，或者不可高速缓存。

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