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11. 发明申请

US20070281489A1 METHODS FOR MINIMIZING MASK UNDERCUTS AND NOTCHES FOR PLASMA PROCESSING SYSTEM 有权
标题翻译：用于最小化等离子体处理系统的掩模和凹槽的方法
公开(公告)号：US20070281489A1
公开(公告)日：2007-12-06
申请号：US11421000
申请日：2006-05-30
申请人： Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
发明人： Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/30655 , B81C1/00571 , H01L21/32137
摘要： A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.
摘要翻译：一种用于蚀刻沉积在等离子体处理室中的底部电极上的衬底的硅层的方法。该方法包括执行主蚀刻步骤，直到至少70％的硅层被蚀刻。该方法还包括一个过程延伸步骤，其包括第一，第二和第三工艺步骤。第一处理步骤采用第一处理配方，第二处理步骤采用第二处理配方，并且第三处理步骤采用第三处理配方。第二工艺配方采用施加到底部电极的第二底部偏置电压电平，该第二底部偏置电压电平高于第一工艺配方中使用的第一底部偏置电压电平，而第三工艺配方中采用第三底部偏置电压电平。第一，第二和第三工艺步骤交替多次，直到硅层被蚀刻通过。

12. 发明申请

US20070141847A1 Notch stop pulsing process for plasma processing system 有权
标题翻译：等离子体处理系统的停止脉冲过程
公开(公告)号：US20070141847A1
公开(公告)日：2007-06-21
申请号：US11305440
申请日：2005-12-16
申请人： Tamarak Pandhumsoporn , Alferd Cofer
发明人： Tamarak Pandhumsoporn , Alferd Cofer
IPC分类号： C03C25/68 , H01L21/461 , H01L21/302 , C03C15/00
CPC分类号： H01L21/30655
摘要： A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.
摘要翻译：一种用于在蚀刻期间蚀刻具有底层电极的等离子体处理室中具有硅层的衬底的方法。该方法包括执行主蚀刻步骤。当达到至少70％的厚度的预定蚀刻深度达到硅层时，该方法还包括终止主蚀刻步骤。所述方法还包括执行过程延展步骤。该疏水步骤包括第一工艺步骤和第二工艺步骤。使用施加到底部电极的第一底部功率电平来执行第一处理步骤。使用低于第一底部功率电平的施加到底部电极的第二底部功率电平来执行第二工艺步骤。交替执行第一处理和第二处理步骤多次。该方法还包括在蚀刻硅层之后终止过蚀刻步骤。

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