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11. 发明授权

US4529476A Gas for selectively etching silicon nitride and process for selectively etching silicon nitride with the gas 失效
标题翻译：用于选择性地蚀刻氮化硅的气体和用气体选择性地蚀刻氮化硅的工艺
公开(公告)号：US4529476A
公开(公告)日：1985-07-16
申请号：US616114
申请日：1984-06-01
申请人： Yoshifumi Kawamoto , Hiroshi Kawakami , Tokuo Kure , Shinichi Tachi , Norikazu Hashimoto , Tsuyoshi Takaichi
发明人： Yoshifumi Kawamoto , Hiroshi Kawakami , Tokuo Kure , Shinichi Tachi , Norikazu Hashimoto , Tsuyoshi Takaichi
IPC分类号： C04B41/53 , C04B41/91 , C09K13/08 , H01L21/311 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： C04B41/009 , C04B41/5346 , C04B41/91 , C09K13/08 , H01L21/31116
摘要： A dry-etching gas suitable for selective etching of silicon nitride and a process for selectively dry-etching silicon nitride with the dry-etching gas are disclosed. Silicon nitride can be dry-etched with a higher selectivity or at a higher etching rate than silicon dioxide and silicon, and a process for fabricating semi-conductor devices can be simplified and devices with a novel structure can be realized.
摘要翻译：公开了适用于选择性蚀刻氮化硅的干蚀刻气体和用干蚀刻气体选择性干蚀刻氮化硅的工艺。可以以比二氧化硅和硅更高的选择性或更高的蚀刻速率干蚀刻氮化硅，并且可以简化制造半导体器件的工艺，并且可以实现具有新颖结构的器件。

12. 发明授权

US4361949A Process for making a memory device 失效
标题翻译：制作存储设备的过程
公开(公告)号：US4361949A
公开(公告)日：1982-12-07
申请号：US269507
申请日：1981-06-01
申请人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
发明人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L27/115 , H01L29/78 , H01L21/22
CPC分类号： H01L27/10844 , H01L21/76877 , H01L21/76897 , H01L27/115
摘要： A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer.Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer.First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.
摘要翻译：包括第一电极的第一半导体电路元件形成在半导体衬底上，在第一电极上形成用于绝缘第一电极的绝缘层，并且在该绝缘层的一部分中设置第一开口。随后，通过形成第二电极形成第二半导体电路元件，该第二电极部分地覆盖除了第一开口之外的区域的绝缘层，并且在第一开口中形成辅助导电层。在由此形成的结构上形成另一绝缘层，于是在后一绝缘层中分别设置第二和第三开口。第一和第二导体分别沉积在第二和第三开口中，由此提供与第一和第二电极的电接触，与第一电极的接触经由辅助导电层。

13. 发明授权

US4270262A Semiconductor device and process for making the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US4270262A
公开(公告)日：1981-06-02
申请号：US880618
申请日：1978-02-23
申请人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
发明人： Ryoichi Hori , Masaharu Kubo , Norikazu Hashimoto , Shigeru Nishimatsu , Kiyoo Itoh
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L27/115 , H01L29/78 , H01L21/70 , H01L21/90
CPC分类号： H01L27/10844 , H01L21/76877 , H01L21/76897 , H01L27/115
摘要： A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.
摘要翻译：包括第一电极的第一半导体电路元件形成在半导体衬底上，在第一电极上形成用于绝缘第一电极的层间绝缘层，并且第一穿透开口设置在层间绝缘体的一部分中层。随后，执行形成第二半导体电路元件的步骤，该步骤包括形成第二电极的步骤，使得其至少一部分可以覆盖除了第一穿透开口之外的区域的层间绝缘层。此外，辅助互连导电层被埋入第一开口中。在由此形成的结构上形成另一绝缘层，由此在第二电极和互连副导电层上的绝缘层中分别设置第二和第三穿透开口。第一和第二互连导体分别埋入第二和第三穿透开口中。第一电极通过第一开口中的辅助互连导电层与第三开口中的第二互连导体导电连接。第二电极与第二开口中的第一互连导体导电连接。

14. 发明授权

US5132752A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5132752A
公开(公告)日：1992-07-21
申请号：US658463
申请日：1991-02-22
申请人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
发明人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
IPC分类号： H01L29/10 , H01L29/812
CPC分类号： H01L29/1075 , H01L29/812 , Y10S257/903
摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
摘要翻译：形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。第二半导体层被掺杂以使其完全耗尽。因此，与衬底相邻的第二半导体层的一部分将保持导电。具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

15. 发明授权

US4805005A Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US4805005A
公开(公告)日：1989-02-14
申请号：US783086
申请日：1985-10-02
申请人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
发明人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
IPC分类号： H01L21/338 , H01L21/8252 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7787 , H01L21/8252 , H01L29/1029 , H01L29/1075 , H01L29/8122
摘要： A semiconductor device and method of manufacturing the same. The device comprises a first n-type semiconductor layer and a second undoped semiconductor layer between which a hetero-junction is formed, and a third p-type embedded semiconductor layer, a gate metal formed without the exposure to air immediately after the third, second and first semiconductor layer are successively formed, and an external electrode connected with the third p-type embedded semiconductor layer, capable of controlling the carriers in the neighborhood of the hetero-junction. This semiconductor device greatly improves the controllability of the threshold voltage thereof, and provides the gate electrodes of good quality.
摘要翻译：一种半导体器件及其制造方法。该器件包括第一n型半导体层和在其之间形成异质结的第二未掺杂半导体层，以及第三p型嵌入式半导体层，在三分之一之后立即形成不暴露于空气的栅极金属，第二并且连续形成第一半导体层，以及与第三p型嵌入式半导体层连接的能够控制异质结附近的载流子的外部电极。该半导体器件极大地提高了其阈值电压的可控性，并且提供质量好的栅电极。

16. 发明授权

US4377819A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4377819A
公开(公告)日：1983-03-22
申请号：US032017
申请日：1979-04-20
申请人： Yoshio Sakai , Toshiaki Masuhara , Osamu Minato , Toshio Sasaki , Hisao Katto , Norikazu Hashimoto , Shin-ichi Muramatsu , Akihiro Tomozawa
发明人： Yoshio Sakai , Toshiaki Masuhara , Osamu Minato , Toshio Sasaki , Hisao Katto , Norikazu Hashimoto , Shin-ichi Muramatsu , Akihiro Tomozawa
IPC分类号： G11C11/412 , H01L21/02 , H01L21/318 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/11 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/04
CPC分类号： H01L29/402 , H01L21/3185 , H01L27/0605 , H01L27/1112 , H01L28/20 , H01L29/41
摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.
摘要翻译：一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。电极与地电位耦合。以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。

17. 发明授权

US4015281A MIS-FETs isolated on common substrate 失效
标题翻译：在公共基板上隔离的MIS-FET
公开(公告)号：US4015281A
公开(公告)日：1977-03-29
申请号：US121375
申请日：1971-03-05
申请人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
发明人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
IPC分类号： H01L21/765 , H01L27/088 , H01L29/51 , H01L27/02
CPC分类号： H01L29/511 , H01L21/765 , H01L27/0883
摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.
摘要翻译：增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

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