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11. 发明申请

US20050285137A1 Semiconductor device with strain 有权
标题翻译：具有应变的半导体器件
公开(公告)号：US20050285137A1
公开(公告)日：2005-12-29
申请号：US10970160
申请日：2004-10-22
申请人： Shigeo Satoh
发明人： Shigeo Satoh
IPC分类号： H01L21/3115 , H01L21/8238 , H01L29/73
CPC分类号： H01L29/7843 , H01L21/31155 , H01L21/823807 , H01L21/823828 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
摘要翻译：半导体器件包括：具有p-MOS区的半导体衬底; 形成在所述半导体衬底的表面部分并限定所述p-MOS区中的p-MOS有源区的元件隔离区; 形成在半导体衬底上方的p-MOS栅极电极结构，穿过p-MOS有源区并在p-MOS栅电极结构下限定p-MOS沟道区; 选择性地形成在p-MOS有源区上方并覆盖p-MOS栅电极结构的压应力膜; 以及选择性地形成在p-MOS区域中的元件隔离区域上方并且释放压缩应力膜中的应力的应力释放区域，其中沿着栅极长度方向的压缩应力和沿着栅极宽度方向的拉伸应力施加在p -MOS通道区域。通过分别对有源区域和元件隔离区域进行控制来提高半导体器件的性能。

12. 发明授权

US08338919B2 Semiconductor device with strain 有权
公开(公告)号：US08338919B2
公开(公告)日：2012-12-25
申请号：US13329606
申请日：2011-12-19
申请人： Shigeo Satoh
发明人： Shigeo Satoh
IPC分类号： H01L27/088 , H01L29/06 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31155 , H01L21/823807 , H01L21/823828 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

13. 发明授权

US08237219B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08237219B2
公开(公告)日：2012-08-07
申请号：US12877882
申请日：2010-09-08
申请人： Akihiro Usujima , Shigeo Satoh
发明人： Akihiro Usujima , Shigeo Satoh
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
摘要翻译：半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁隔离物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

14. 发明申请

US20120161230A1 MOS TRANSISTOR AND FABRICATION METHOD THEREOF 有权
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US20120161230A1
公开(公告)日：2012-06-28
申请号：US13270661
申请日：2011-10-11
申请人： Shigeo Satoh , Takae Sukegawa
发明人： Shigeo Satoh , Takae Sukegawa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/66545 , H01L29/66689 , H01L29/7831
摘要： A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.
摘要翻译：所公开的MOS晶体管具有从栅电极结构偏移的漏区，其中栅电极结构至少包括第一栅电极和第二栅电极，使得第二栅电极位于第一栅电极的漏极侧，第二栅电极通过绝缘膜与第一栅电极隔离，并且其中第一和第二栅电极分别形成在与第一栅极绝缘体相比具有增加的厚度的第一栅绝缘膜和第二栅绝缘膜上电影。

15. 发明申请

US20110018067A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110018067A1
公开(公告)日：2011-01-27
申请号：US12833279
申请日：2010-07-09
申请人： Akihiro Usujima , Shigeo Satoh
发明人： Akihiro Usujima , Shigeo Satoh
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823878
摘要： A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.
摘要翻译：一种制造半导体器件的方法包括：形成第一隔离绝缘膜和第二隔离绝缘膜，以限定第一，第二，第三和第四区域，形成第一绝缘膜，通过第一和第二区域注入第一导电类型的第一杂质; 在第一深度处将第一，第二和第四区域的绝缘膜形成为比第一绝缘膜更薄的第二绝缘膜，在第二绝缘膜中将第二导电类型的第二杂质通过第二绝缘膜注入第三区域深度在所述半导体衬底中，在比所述第二深度浅的第三深度处将第二导电类型的第三杂质注入所述第三区域，在所述第三区域中形成所述第一导电类型的第一晶体管，以及形成所述第二晶体管，第四区域的第二导电类型。

16. 发明申请

US20080296635A1 Semiconductor device with strain 有权
公开(公告)号：US20080296635A1
公开(公告)日：2008-12-04
申请号：US12219882
申请日：2008-07-30
申请人： Shigeo Satoh
发明人： Shigeo Satoh
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/31155 , H01L21/823807 , H01L21/823828 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

17. 发明申请

US20070001245A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070001245A1
公开(公告)日：2007-01-04
申请号：US11071119
申请日：2005-03-04
申请人： Shigeo Satoh , Masataka Kase
发明人： Shigeo Satoh , Masataka Kase
IPC分类号： H01L29/94
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/28052 , H01L21/32155 , H01L21/823814 , H01L21/823842 , H01L29/665 , H01L29/6659
摘要： An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.
摘要翻译：在使用过蚀刻的侧壁作为掩模的同时，沿着与所述半导体衬底的表面倾斜的方向将栅极电极的暴露表面注入与源极 - 漏极区域中所包含的导电类型相同的杂质，其中栅电极在其一个侧面的顶表面和上部注入，而源极和漏极区中的一个以可能通过单次注入的量注入杂质，而另一部分没有植入或只是稍微植入到较少的情感程度。

18. 发明申请

US20050287756A1 Semiconductor device with resistor element and its manufacture method 有权
标题翻译：具有电阻元件的半导体器件及其制造方法
公开(公告)号：US20050287756A1
公开(公告)日：2005-12-29
申请号：US10950451
申请日：2004-09-28
申请人： Kaina Suzuki , Shigeo Satoh
发明人： Kaina Suzuki , Shigeo Satoh
IPC分类号： H01L21/02 , H01L21/20 , H01L21/762 , H01L27/01 , H01L27/06 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/76229 , H01L27/0629 , H01L28/20
摘要： A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.
摘要翻译：第一阱形成在半导体衬底的表面层中，第一层是第一导电型，第一阱是与第一导电类型相反的第二导电类型。一对当前输入/输出端口连接到第一阱，该对电流输入/输出端口用于沿着平行于衬底表面的方向流过第一阱的电流。第一导电类型的第二阱设置在一对电流输入/输出端口之间，第二阱比第一阱浅。提供了一种有助于具有所需电阻值的电阻元件。

19. 发明授权

US4703628A Apparatus for preparing frozen products 失效
标题翻译：用于制备冷冻产品的装置
公开(公告)号：US4703628A
公开(公告)日：1987-11-03
申请号：US763405
申请日：1985-08-07
申请人： Shigeru Togashi , Hiromi Saitoh , Shigeyuki Takahashi , Yasuo Makino , Mitsuru Kakinuma , Shigeo Satoh , Shigeki Sugiyama
发明人： Shigeru Togashi , Hiromi Saitoh , Shigeyuki Takahashi , Yasuo Makino , Mitsuru Kakinuma , Shigeo Satoh , Shigeki Sugiyama
IPC分类号： A23G9/16 , A23G9/22 , A23G9/30 , F25D19/04 , F25C1/00 , A23G9/00
CPC分类号： F25D19/04 , A23G9/163 , A23G9/228 , A23G9/30
摘要： An apparatus for preparing frozen products having a mix tank, a freezing chamber, a liquid mix supply means, a dispensing device, a freezing means for the freezing chamber comprising independent first and second freezing systems, and a frozen control means comprising a first and second frozen control means for said first and second freezing systems respectively, and making it possible that liquid mix in the freezing chamber may be always frozen in good condition. Further an apparatus for preparing frozen products having a frozen and chilled control means for the freezing means independently, and making it possible that liquid mix is stored in the freezing chamber when the freezing operation does not occur.
摘要翻译：一种用于制备具有混合罐，冷冻室，液体混合物供应装置，分配装置，用于包括独立的第一和第二冷冻系统的冷冻室的冷冻装置的冷冻产品的装置，以及包括第一和第二冷冻装置的冷冻控制装置分别用于所述第一和第二冷冻系统的冷冻控制装置，并且使冷冻室中的液体混合可能总是在良好状态下被冷冻。此外，一种用于制备具有用于冷冻装置的冷冻和冷冻控制装置的冷冻产品的装置，并且当不发生冷冻操作时，可以将液体混合物储存在冷冻室中。

20. 发明授权

US08637929B2 LDMOS transistor having a gate electrode formed over thick and thin portions of a gate insulation film 有权
标题翻译： LDMOS晶体管具有形成在栅极绝缘膜的厚薄部分上的栅电极
公开(公告)号：US08637929B2
公开(公告)日：2014-01-28
申请号：US13270661
申请日：2011-10-11
申请人： Shigeo Satoh , Takae Sukegawa
发明人： Shigeo Satoh , Takae Sukegawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/66545 , H01L29/66689 , H01L29/7831
摘要： A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.
摘要翻译：所公开的MOS晶体管具有从栅电极结构偏移的漏区，其中栅电极结构至少包括第一栅电极和第二栅电极，使得第二栅电极位于第一栅电极的漏极侧，第二栅电极通过绝缘膜与第一栅电极隔离，并且其中第一和第二栅电极分别形成在与第一栅极绝缘体相比具有增加的厚度的第一栅极绝缘膜和第二栅极绝缘膜上电影。

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