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11. 发明授权

US08813876B2 Downhole tool impact dissipating tool 有权
标题翻译：井下工具冲击消散工具
公开(公告)号：US08813876B2
公开(公告)日：2014-08-26
申请号：US13276076
申请日：2011-10-18
申请人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
发明人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
IPC分类号： E21B17/10
CPC分类号： E21B17/07
摘要： An impact dissipation tool for supporting a downhole tool in downhole applications. The tool includes a base and a housing. The tool also includes a carriage located within the housing and coupled to the base, the carriage being movable relative to the housing upon a predetermined impact force. A dissipator disposed inside the housing is collapsible due to the relative movement of the carriage and the housing. The collapse of the dissipator dissipates the impact force transferred to the downhole tool.
摘要翻译：用于在井下应用中支撑井下工具的冲击耗散工具。该工具包括底座和外壳。工具还包括位于壳体内并联接到基座的滑架，滑架可在预定的冲击力下相对于壳体移动。由于托架和壳体的相对移动，设置在壳体内部的耗散器可折叠。耗散器的塌陷消散了传递到井下工具的冲击力。

12. 发明申请

US20100096187A1 THROUGH DRILLSTRING LOGGING SYSTEMS AND METHODS 有权
标题翻译：通过钻探记录系统和方法
公开(公告)号：US20100096187A1
公开(公告)日：2010-04-22
申请号：US12582520
申请日：2009-10-20
申请人： Bruce H. Storm, JR. , James G. Aivalis , Bulent Finci , Peter Wells , Akio Kita , Eric Johnson , Jonathan Macrae
发明人： Bruce H. Storm, JR. , James G. Aivalis , Bulent Finci , Peter Wells , Akio Kita , Eric Johnson , Jonathan Macrae
IPC分类号： E21B47/12
CPC分类号： E21B10/62 , E21B23/14 , E21B47/01
摘要： Embodiments of the present invention generally relate to methods and systems for logging through a drillstring. In one embodiment, a method of logging an exposed formation includes drilling a wellbore by rotating a cutting tool disposed on an end of a drillstring and injecting drilling fluid through the drillstring; deploying a BHA through the drillstring, the BHA including a logging tool; forming a bore through the cutting tool; inserting the logging tool through the bore; longitudinally connecting the BHA to the drillstring; and logging the exposed formation using the logging tool while tripping the drillstring into or from the wellbore.
摘要翻译：本发明的实施例一般涉及用于通过钻柱进行记录的方法和系统。在一个实施例中，记录暴露地层的方法包括通过旋转设置在钻柱端部上的切割工具并通过钻柱注射钻井液来钻井井; 通过钻柱部署BHA，BHA包括测井工具; 通过所述切削工具形成孔; 将测井工具插入孔中; 将BHA纵向连接到钻柱; 并使用测井工具记录暴露的地层，同时将钻柱从钻井中钻出或从井筒跳闸。

13. 发明授权

US4596071A Method of making semiconductor devices having dielectric isolation regions 失效
标题翻译：制造具有绝缘隔离区域的半导体器件的方法
公开(公告)号：US4596071A
公开(公告)日：1986-06-24
申请号：US640833
申请日：1984-08-15
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L21/76 , H01L21/31 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76294 , H01L21/31055
摘要： A method of making semiconductor devices having fine dielectric element isolation regions is disclosed. The method comprises the steps of preparing a semiconductor substrate of one conductivity type which is in a high impurity concentration; forming on the surface of the semi-conductor substrate an epitaxial layer having the same conductivity type as that of the semiconductor substrate in a low impurity concentration; etching off selected regions of the epitaxial layer so as to form islands of the epitaxial layer; forming a CVD oxide layer all over the surface of the structure obtained by the steps; applying high-molecular material film all over the surface of the oxide layer; and removing both the oxide layer and the high-molecular material film so as to expose the surface of the islands, whereby fine element isolation regions of the oxide layer are obtained between the islands.
摘要翻译：公开了一种制造具有精细电介质元件隔离区域的半导体器件的方法。该方法包括制备高杂质浓度的一种导电型半导体衬底的步骤; 在半导体衬底的表面上形成具有与半导体衬底相同导电类型的外延层，其杂质浓度低; 蚀刻所述外延层的选定区域以形成所述外延层的岛; 在通过该步骤获得的结构的整个表面上形成CVD氧化物层; 在氧化物层的整个表面上施加高分子材料膜; 并且除去氧化物层和高分子材料膜以暴露岛的表面，由此在岛之间获得氧化物层的微细元素隔离区。

14. 发明申请

US20170145758A1 DOWNHOLE TOOL IMPACT DISSIPATING TOOL 审中-公开
公开(公告)号：US20170145758A1
公开(公告)日：2017-05-25
申请号：US15428633
申请日：2017-02-09
申请人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
发明人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
IPC分类号： E21B17/07
CPC分类号： E21B17/07
摘要： An impact dissipation tool for supporting a downhole tool in downhole applications. The tool includes a base and a housing. The tool also includes a carriage located within the housing and coupled to the base, the carriage being movable relative to the housing upon a predetermined impact force. A dissipator disposed inside the housing is collapsible due to the relative movement of the carriage and the housing. The collapse of the dissipator dissipates the impact force transferred to the downhole tool.

15. 发明授权

US08443915B2 Through drillstring logging systems and methods 有权
标题翻译：通过钻柱测井系统和方法
公开(公告)号：US08443915B2
公开(公告)日：2013-05-21
申请号：US12582520
申请日：2009-10-20
申请人： Bruce H. Storm, Jr. , James G. Aivalis , Bulent Finci , Peter Wells , Akio Kita , Eric Johnson , Jonathan Macrae
发明人： Bruce H. Storm, Jr. , James G. Aivalis , Bulent Finci , Peter Wells , Akio Kita , Eric Johnson , Jonathan Macrae
IPC分类号： E21B47/01
CPC分类号： E21B10/62 , E21B23/14 , E21B47/01
摘要： Embodiments of the present invention generally relate to methods and systems for logging through a drillstring. In one embodiment, a method of logging an exposed formation includes drilling a wellbore by rotating a cutting tool disposed on an end of a drillstring and injecting drilling fluid through the drillstring; deploying a BHA through the drillstring, the BHA including a logging tool; forming a bore through the cutting tool; inserting the logging tool through the bore; longitudinally connecting the BHA to the drillstring; and logging the exposed formation using the logging tool while tripping the drillstring into or from the wellbore.
摘要翻译：本发明的实施例一般涉及用于通过钻柱进行记录的方法和系统。在一个实施例中，记录暴露地层的方法包括通过旋转设置在钻柱端部上的切割工具并通过钻柱注射钻井液来钻井井; 通过钻柱部署BHA，BHA包括测井工具; 通过所述切削工具形成孔; 将测井工具插入孔中; 将BHA纵向连接到钻柱; 并使用测井工具记录暴露的地层，同时将钻柱从钻井中钻出或从井筒跳闸。

16. 发明授权

US06218257B1 Method of forming semiconductor memory device 失效
标题翻译：形成半导体存储器件的方法
公开(公告)号：US06218257B1
公开(公告)日：2001-04-17
申请号：US09007835
申请日：1998-01-15
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L2120
CPC分类号： H01L28/87 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L27/10814 , H01L28/88 , H01L28/91 , H01L28/92
摘要： Since the capacitor of the semiconductor memory has the storage electrode comprising a shape of the cylindrical structure having rough polysilicon portions on base and sidewall portions thereof, it can increase electrostatic capacitance. Further, since the rough portions of the base and sidewall rough storage electrode layers are respectively formed by independently controlling a condition of Chemical Vapor Deposition, it can easily control formations of the rugged portions of the capacitor, therefore it can achieve the improvement of the productivity of the rough portions. Accordingly, the semiconductor can achieve a stability of a memory operation.
摘要翻译：由于半导体存储器的电容器具有包括其基底和侧壁部分上具有粗多晶硅部分的圆柱形结构的形状的存储电极，因此可以增加静电电容。此外，由于通过独立地控制化学气相沉积的条件分别形成基底和侧壁粗糙储存电极层的粗糙部分，所以可以容易地控制电容器的凹凸部分的形成，从而可以实现生产率的提高的粗糙部分。因此，半导体可以实现存储器操作的稳定性。

17. 发明授权

US5442211A One-transistor one-capacitor memory cell structure for DRAMs 失效
标题翻译：用于DRAM的单晶体管单电容存储单元结构
公开(公告)号：US5442211A
公开(公告)日：1995-08-15
申请号：US156620
申请日：1993-11-23
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/68
CPC分类号： H01L27/10861 , H01L21/76251 , H01L27/10829 , H01L27/1203
摘要： A one-transistor one-capacitor memory cell structure is formed using the following steps. In a first step, a buried insulating film layer is formed in a semiconductor substrate and a semiconductor thin film layer is formed on the buried insulating film layer. In a second step, a capacitor trench is formed in the semiconductor substrate by penetrating through the buried layer and a dielectric film layer is formed on an inner side wall surface of the trench. Then, a conductive material is filled into the trench to form a capacitor. Finally, a MIS transistor is formed in the semiconductor thin film layer adjacent to the trench capacitor such that either the drain or the source makes contact with the conductive material.
摘要翻译：使用以下步骤形成单晶体管单电容器存储单元结构。在第一步骤中，在半导体衬底中形成掩埋绝缘膜层，并在掩埋绝缘膜层上形成半导体薄膜层。在第二步骤中，通过穿过掩埋层在半导体衬底中形成电容器沟槽，并且在沟槽的内侧壁表面上形成电介质膜层。然后，将导电材料填充到沟槽中以形成电容器。最后，在与沟槽电容器相邻的半导体薄膜层中形成MIS晶体管，使得漏极或源极与导电材料接触。

18. 发明授权

US5028554A Process of fabricating an MIS FET 失效
标题翻译：制造MIS FET的过程
公开(公告)号：US5028554A
公开(公告)日：1991-07-02
申请号：US347927
申请日：1989-05-05
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L21/336 , H01L29/45 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/456 , H01L29/78 , H01L29/665 , Y10S148/105 , Y10S148/147
摘要： An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lightly-doped region and the resultant degradation in the characteristic are eliminated.
摘要翻译： LDD MIS FET包括在轻掺杂区域上的硅化物以减少寄生电阻并防止轻掺杂区域的耗尽，减少热载流子注入效应。通过提供硅化物，可以使整体寄生电阻较低。此外，由于负电荷被捕获在轻掺杂区域上的氧化物膜的界面处或在氧化物膜上的轻掺杂区域的电阻的增加以及由此导致的特性降低。

19. 发明授权

US4735915A Method of manufacturing a semiconductor random access memory element 失效
标题翻译：制造半导体随机存取存储元件的方法
公开(公告)号：US4735915A
公开(公告)日：1988-04-05
申请号：US884667
申请日：1986-07-16
申请人： Akio Kita , Masayoshi Ino
发明人： Akio Kita , Masayoshi Ino
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/04 , H01L21/22
CPC分类号： H01L27/1085 , H01L27/10805
摘要： The semiconductor memory element comprises two capacitors and a switching MOS transistor. A first capacitor is constituted by a silicon semiconductor substrate, a thin oxide film and a first doped polycrystalline silicon layer, and a second capacitor is constituted by a second doped polycrystalline silicon layer, a thin oxide film between the first and the second doped polycrystalline silicon layers, and the first polycrystalline silicon layer. Interconnection layers necessary to form a single transistor type dynamic memory cell are also provided.
摘要翻译：半导体存储元件包括两个电容器和开关MOS晶体管。第一电容器由硅半导体衬底，薄氧化物膜和第一掺杂多晶硅层构成，第二电容器由第二掺杂多晶硅层，第一和第二掺杂多晶硅之间的薄氧化膜构成层和第一多晶硅层。还提供了形成单晶体管型动态存储单元所需的互连层。

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