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11. 发明申请

US20110240560A1 Method of adsorbing transforming growth factor ß 审中-公开
标题翻译：吸附转化生长因子的方法
公开(公告)号：US20110240560A1
公开(公告)日：2011-10-06
申请号：US13067627
申请日：2011-06-15
申请人： Kazuo Teramoto , Toshio Yoshioka , Masaaki Shimagaki , Takeo Matsunase , Koji Watanabe , Yuji Ueda , Yoshiki Yamamoto
发明人： Kazuo Teramoto , Toshio Yoshioka , Masaaki Shimagaki , Takeo Matsunase , Koji Watanabe , Yuji Ueda , Yoshiki Yamamoto
IPC分类号： B01D15/00
CPC分类号： B01J20/26 , A61M1/3679 , B01J20/261 , B01J20/262 , B01J20/265 , B01J20/28014 , B01J20/28016 , B01J20/28023 , B01J20/2803 , B01J20/28033 , B01J20/28045 , B01J20/28057 , B01J20/3092 , B01J20/321 , B01J20/3212 , B01J20/3217 , B01J20/3242 , B01J20/3251 , B01J20/3272 , B01J20/3293 , B01J2220/58 , B01J2220/60
摘要： An adsorbent for immunosuppressive substance, which can adsorb an excessive immunosuppressive substance directly from a body fluid, can carry out extracorporeal perfusion safely and can be utilized in treatment of cancer. The excessive immunosuppressive substance may be involved in growth of cancer cells. The adsorbent for immunosuppressive substance includes a water-insoluble carrier and a hydrophilic amino group immobilized to the water-insoluble carrier. An extracorporeal perfusion column contains the adsorbent of the invention. A method for treating cancer carries out extracorporeal perfusion using the extracorporeal perfusion column. A method of adsorbing the transforming growth factor β which is combined with another protein, includes adsorbing the transforming growth factor β and protein on an adsorbent containing a water-insoluble carrier to which quaternary ammonium groups each having 3 to 18 carbon atoms per one nitrogen atom are attached, and having a specific surface area of 0.1 m2 or more per gram.
摘要翻译：可以直接从体液吸附过量免疫抑制物质的免疫抑制物质吸附剂可以安全地进行体外灌注，可用于治疗癌症。过量的免疫抑制物质可能参与癌细胞的生长。用于免疫抑制物质的吸附剂包括固定在水不溶性载体上的水不溶性载体和亲水性氨基。体外灌注柱包含本发明的吸附剂。一种治疗癌症的方法使用体外灌注柱进行体外灌注。吸附转化生长因子的方法其与另一种蛋白质组合，包括吸收转化生长因子和bgr; 和含有每个氮原子上具有3〜18个碳原子的季铵基的水不溶性载体的吸附剂上的蛋白质，并且比表面积为0.1m 2以上。

12. 发明授权

US09293347B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US09293347B2
公开(公告)日：2016-03-22
申请号：US14381562
申请日：2012-05-18
申请人： Yoshiki Yamamoto , Hideki Makiyama , Takaaki Tsunomura , Toshiaki Iwamatsu
发明人： Yoshiki Yamamoto , Hideki Makiyama , Takaaki Tsunomura , Toshiaki Iwamatsu
IPC分类号： H01L21/32 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/786
CPC分类号： H01L21/32 , H01L29/0847 , H01L29/42376 , H01L29/42384 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/7836 , H01L29/7848 , H01L29/786 , H01L29/78618 , H01L29/78627
摘要： The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.

13. 发明授权

US08361255B2 Copper alloy material and method of making same 失效
标题翻译：铜合金材料及其制造方法
公开(公告)号：US08361255B2
公开(公告)日：2013-01-29
申请号：US12603804
申请日：2009-10-22
申请人： Hiroaki Takano , Yoshiki Yamamoto , Koichi Kotoku , Chingping Tong
发明人： Hiroaki Takano , Yoshiki Yamamoto , Koichi Kotoku , Chingping Tong
IPC分类号： C22F1/08 , C22C9/06
CPC分类号： C22C9/06 , C22C9/04 , C22F1/08
摘要： A copper alloy material having: 1.0 to 5.0 mass % of Ni; 0.2 to 1.0 mass % of Si; 1.0 to 5.0 mass % of Zn; 0.1 to 0.5 mass % of Sn; 0.003 to 0.3 mass % of P; and the balance consisting of Cu and an unavoidable impurity. The mass ratio between Ni and each of Si, Zn and Sn is to be Ni/Si=4 to 6, Zn/Ni=0.5 or more, and Sn/Ni=0.05 to 0.2.
摘要翻译：具有1.0〜5.0质量％的Ni的铜合金材料; Si：0.2〜1.0质量％ 1.0〜5.0质量％的Zn; Sn：0.1〜0.5质量％ 0.003〜0.3质量％余量由Cu和不可避免的杂质组成。 Ni与Si，Zn，Sn的质量比为Ni / Si = 4〜6，Zn / Ni = 0.5以上，Sn / Ni = 0.05〜0.2。

14. 发明申请

US20120193726A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120193726A1
公开(公告)日：2012-08-02
申请号：US13500863
申请日：2009-10-06
申请人： Tomohiro Yamashita , Yukio Nishida , Takashi Hayashi , Yoshiki Yamamoto , Masao Inoue
发明人： Tomohiro Yamashita , Yukio Nishida , Takashi Hayashi , Yoshiki Yamamoto , Masao Inoue
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/02181 , H01L21/02192 , H01L21/02194 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： A semiconductor device including an n-channel-type MISFET (Qn) having an Hf-containing insulating film (5), which is a high dielectric constant gate insulating film containing hafnium, a rare-earth element, and oxygen as main components, and a gate electrode (GE1), which is a metal gate electrode, is manufactured. The Hf-containing insulating film (5) is formed by forming a first Hf-containing film containing hafnium and oxygen as main components, a rare-earth containing film containing a rare-earth element as a main component, and a second Hf-containing film containing hafnium and oxygen as main components sequentially from below and then causing these to react with one another.
摘要翻译：包括具有含Hf的绝缘膜（5）的n沟道型MISFET（Qn）的半导体器件，其是含有铪，稀土元素和氧作为主要成分的高介电常数栅极绝缘膜，以及制造作为金属栅电极的栅电极（GE1）。含Hf绝缘膜（5）通过形成含有铪和氧作为主要成分的第一含Hf膜，含有稀土元素作为主要成分的稀土类膜，第二Hf含从下面顺序地含有铪和氧作为主要成分的膜，然后使它们彼此反应。

15. 发明申请

US20100102395A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100102395A1
公开(公告)日：2010-04-29
申请号：US12572646
申请日：2009-10-02
申请人： Yoshiki Yamamoto , Yukio Nishida , Jiro Yugami
发明人： Yoshiki Yamamoto , Yukio Nishida , Jiro Yugami
IPC分类号： H01L27/092 , H01L21/28 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823857
摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.
摘要翻译：提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜，栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

16. 发明申请

US20100037996A1 COPPER ALLOY MATERIAL AND METHOD OF MAKING SAME 失效
标题翻译：铜合金材料及其制备方法
公开(公告)号：US20100037996A1
公开(公告)日：2010-02-18
申请号：US12603804
申请日：2009-10-22
申请人： Hiroaki TAKANO , Yoshiki Yamamoto , Koichi Kotoku , Chingping Tong
发明人： Hiroaki TAKANO , Yoshiki Yamamoto , Koichi Kotoku , Chingping Tong
IPC分类号： C22F1/08
CPC分类号： C22C9/06 , C22C9/04 , C22F1/08
摘要： A copper alloy material having: 1.0 to 5.0 mass % of Ni; 0.2 to 1.0 mass % of Si; 1.0 to 5.0 mass % of Zn; 0.1 to 0.5 mass % of Sn; 0.003 to 0.3 mass % of P; and the balance consisting of Cu and an unavoidable impurity. The mass ratio between Ni and each of Si, Zn and Sn is to be Ni/Si=4 to 6, Zn/Ni=0.5 or more, and Sn/Ni=0.05 to 0.2.
摘要翻译：具有1.0〜5.0质量％的Ni的铜合金材料; Si：0.2〜1.0质量％ 1.0〜5.0质量％的Zn; Sn：0.1〜0.5质量％ 0.003〜0.3质量％余量由Cu和不可避免的杂质组成。 Ni与Si，Zn，Sn的质量比为Ni / Si = 4〜6，Zn / Ni = 0.5以上，Sn / Ni = 0.05〜0.2。

17. 发明授权

US5655050A Apparatus and method for recording and reproducing digital signal in synchronization blocks 失效
标题翻译：用于在同步块中记录和再现数字信号的装置和方法
公开(公告)号：US5655050A
公开(公告)日：1997-08-05
申请号：US659623
申请日：1996-06-06
申请人： Yoshiki Yamamoto , Tetsuya Mizushima , Akira Iketani , Yasunori Kawakami , Chiyoko Matsumi
发明人： Yoshiki Yamamoto , Tetsuya Mizushima , Akira Iketani , Yasunori Kawakami , Chiyoko Matsumi
IPC分类号： G11B20/12 , G11B5/008 , G11B5/09 , G11B20/18 , G11B27/28 , G11B27/30 , H04N5/926 , H04N5/935 , H04N5/945 , H04N5/76
CPC分类号： G11B20/1208 , G11B27/3027 , H04N5/9261 , H04N5/935 , G11B20/1833 , G11B2220/90 , G11B5/0086 , G11B5/09 , H04N5/945
摘要： A digital signal recording apparatus for recording digital signal in synchronization blocks includes a generator for generating a synchronization pattern for indicating the beginning of each synchronization block, a generator for generating an ID data for indicating the sequence of the synchronization blocks, a generator for generating an ID parity for checking the ID data, a generator for generating additional information signal, which is a track width data, a generator for generating audio and video signals. Above data are applied to a pattern generator for generating track data comprising plural consecutive normal synchronization blocks immediately preceded by two mini-synchronization blocks and immediately followed by one mini-synchronization block. Each mini-synchronization block includes the synchrionization pattern, ID data, ID parity, and additional information signal. Each normal synchronization block includes the synchronization pattern, ID data, ID parity, and audio and video signal.
摘要翻译：用于在同步块中记录数字信号的数字信号记录装置包括用于产生用于指示每个同步块的开始的同步模式的发生器，用于产生用于指示同步块的序列的ID数据的发生器，用于生成用于检查ID数据的ID奇偶校验，用于产生作为轨道宽度数据的附加信息信号的发生器，用于产生音频和视频信号的发生器。上述数据被应用于模式发生器，用于产生包括紧接在两个小型同步块之前的多个连续正常同步块的跟踪数据，并且紧随其后的是一个小型同步块。每个小型同步块包括同步模式，ID数据，ID奇偶校验和附加信息信号。每个正常同步块包括同步模式，ID数据，ID奇偶校验以及音频和视频信号。

18. 发明授权

US09202761B2 Semiconductor integrated circuit device and manufacturing method for semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US09202761B2
公开(公告)日：2015-12-01
申请号：US13620986
申请日：2012-09-15
申请人： Hideki Makiyama , Yoshiki Yamamoto
发明人： Hideki Makiyama , Yoshiki Yamamoto
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66 , H01L21/8238
CPC分类号： H01L27/1207 , H01L21/76283 , H01L21/823814 , H01L21/82385 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0684 , H01L29/42356 , H01L29/66545
摘要： The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
摘要翻译：半导体集成电路器件具有在半导体衬底的器件平面侧包括SOI结构和体结构的混合衬底结构。在器件中，SOI型MISFET的栅电极的高度高于相对于器件平面的体型MISFET的栅电极的高度。

19. 发明授权

US08796780B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08796780B2
公开(公告)日：2014-08-05
申请号：US12572646
申请日：2009-10-02
申请人： Yoshiki Yamamoto , Yukio Nishida , Jiro Yugami
发明人： Yoshiki Yamamoto , Yukio Nishida , Jiro Yugami
IPC分类号： H01L29/72
CPC分类号： H01L21/823828 , H01L21/823857
摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.
摘要翻译：提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜，以及栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

20. 发明申请

US20100319818A1 Method for fabricating a copper alloy and copper alloy fabricated by the same 审中-公开
标题翻译：制造铜合金和铜合金的方法
公开(公告)号：US20100319818A1
公开(公告)日：2010-12-23
申请号：US12801278
申请日：2010-06-01
申请人： Yoshiki Sawai , Yoshiki Yamamoto , Noboru Hagiwara
发明人： Yoshiki Sawai , Yoshiki Yamamoto , Noboru Hagiwara
IPC分类号： C22F1/08 , C22C9/00 , C21D8/00 , C22C9/02
CPC分类号： C22C9/00 , C22C9/02 , C22F1/08
摘要： A method for fabricating a copper alloy. Cu and Cr, Zr, and Sn to be doped to the Cu are melt to cast a copper alloy material. Hot working is carried out on the copper alloy material to form a plate material having a rolled texture. Heat treatment is carried out on the plate material. Cold rolling with workability of 80% or more and less than 90% is carried out on the plate material after the heat treatment to form an intermediate plate material. Aging treatment is carried out on the intermediate plate material. Another cold rolling with workability of 20% to 40% is carried out as finish rolling on the intermediate plate material after the aging treatment step. The intermediate plate material after the finish rolling step is heated as stress relief annealing.
摘要翻译：一种铜合金的制造方法。将要掺杂到Cu的Cu和Cr，Zr和Sn熔融铸造铜合金材料。在铜合金材料上进行热加工以形成具有轧制质地的板材。在板材上进行热处理。在热处理后，在板材上进行加工性为80％以上且小于90％的冷轧，形成中间板材。在中间板材上进行老化处理。在老化处理步骤之后，对中间板材进行精轧，进行另外的加工性为20％〜40％的冷轧。将精轧工序后的中间板材作为应力消除退火进行加热。

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