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11. 发明申请

US20050213414A1 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US20050213414A1
公开(公告)日：2005-09-29
申请号：US11131181
申请日：2005-05-18
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G11C5/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/20
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

12. 发明授权

US06281711B1 Semiconductor integrated circuit device having power reduction mechanism 有权
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06281711B1
公开(公告)日：2001-08-28
申请号：US09291977
申请日：1999-04-15
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

13. 发明授权

US07750668B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有降压机构的半导体集成电路装置
公开(公告)号：US07750668B2
公开(公告)日：2010-07-06
申请号：US11979100
申请日：2007-10-31
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19/003 , G05F1/10 , G06F1/32
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

14. 发明授权

US06175251B1 Semiconductor integrated circuit device having power reduction 有权
标题翻译：具有功率降低的半导体集成电路器件
公开(公告)号：US06175251B1
公开(公告)日：2001-01-16
申请号：US09291957
申请日：1999-04-15
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K190948
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

15. 发明授权

US06504402B2 Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US06504402B2
公开(公告)日：2003-01-07
申请号：US10051013
申请日：2002-01-22
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

16. 发明授权

US6046604A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US6046604A
公开(公告)日：2000-04-04
申请号：US123480
申请日：1998-07-28
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G11C5/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/20
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H03K19/0013 , H03K19/0016 , H03K19/01721 , H03K3/356113 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

17. 发明授权

US5828235A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US5828235A
公开(公告)日：1998-10-27
申请号：US653248
申请日：1996-05-24
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G11C5/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/20 , H03K19/948
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H03K19/0013 , H03K19/0016 , H03K19/01721 , H03K3/356113 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

18. 发明授权

US5528548A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5528548A
公开(公告)日：1996-06-18
申请号：US384962
申请日：1995-02-07
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：提供一种半导体存储器，其包括电压转换器，其向半导体存储器中的电路提供与两个参考电压中的较大一个成比例的内部电源电压。电压转换器包括电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一电路用于产生对外部供电电压的依赖性大于第一电压的依赖性。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压电路。该存储器还包括用于升高内部电源电压的字线升压器。

19. 发明授权

US5272393A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5272393A
公开(公告)日：1993-12-21
申请号：US790065
申请日：1991-11-12
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , H03K3/01 , H03K5/22
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.
摘要翻译：在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

20. 发明授权

US5402375A Voltage converter arrangement for a semiconductor memory 失效
标题翻译：用于半导体存储器的电压转换器装置
公开(公告)号：US5402375A
公开(公告)日：1995-03-28
申请号：US207679
申请日：1994-03-09
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：在设置在半导体存储器中的电压转换器中并向半导体存储器中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压装置。该存储器还包括用于升高内部电源电压的字线升压器。

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