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11. 发明申请

US20130007758A1 MULTI-CORE PROCESSOR SYSTEM, THREAD SWITCHING CONTROL METHOD, AND COMPUTER PRODUCT 审中-公开
标题翻译：多核处理器系统，线程切换控制方法和计算机产品
公开(公告)号：US20130007758A1
公开(公告)日：2013-01-03
申请号：US13614071
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/4825 , G06F2209/486
摘要： A multi-core processor system includes a given core configured to switch at a prescribed switching period, threads assigned to the given core; identify whether the given core has switched threads at a period exceeding the prescribed switching period; correct the prescribed switching period into a shorter switching period, based on a difference of an actual switching period at which the threads have been switched by the given core and the prescribed switching period; and set the corrected switching period as the prescribed switching period.
摘要翻译：多核处理器系统包括被配置为在规定的切换周期切换的给定核心，分配给给定核心的线程; 确定给定的核心是否在超过规定的切换周期的时间段内切换了线程; 基于由给定核心切换线程的实际切换周期与规定切换周期之间的差异，将规定的切换周期更正为更短的切换周期; 并将修正的开关周期设定为规定的切换期间。

12. 发明申请

US20130007439A1 MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND NOTIFICATION METHOD 有权
标题翻译：多重处理器系统，计算机产品和通知方法
公开(公告)号：US20130007439A1
公开(公告)日：2013-01-03
申请号：US13613605
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/06
CPC分类号： G06F9/4405 , G06F9/441
摘要： A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change.
摘要翻译：多核处理器系统包括处理器，其配置成在多核处理器中用旧引导程序引导的核心之间检测不分配进程的核心; 在检测到没有分配处理的核心的情况下，从旧的引导程序的存储区域到用于新的引导程序的存储区域的参考区域; 并且在更改之后通知指定了指定参考区域的重新引导指令没有进程的核心。

13. 发明申请

US20130013834A1 MULTI-CORE PROCESSOR SYSTEM, ARBITER CIRCUIT CONTROL METHOD, AND COMPUTER PRODUCT 有权
标题翻译：多核处理器系统，ARBITER电路控制方法和计算机产品
公开(公告)号：US20130013834A1
公开(公告)日：2013-01-10
申请号：US13613634
申请日：2012-09-13
申请人： Koichiro YAMASHITA , Hiromasa Yamauchi
发明人： Koichiro YAMASHITA , Hiromasa Yamauchi
IPC分类号： G06F13/14
CPC分类号： G06F9/5083 , G06F9/5016 , G06F13/16 , G06F13/1605 , G06F13/1652
摘要： A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights.
摘要翻译：多核处理器系统包括多个核心; 由内核访问的共享内存; 以及仲裁电路，其仲裁由核心访问共享存储器的权限的争用。每个核心被配置为获取核心，测量到共享存储器的访问速度; 计算核心，基于测量的访问速度和核心访问理论速度的响应性能; 计算核心，并根据为每个核心计算的响应性能，访问共享内存的访问权限的比例，计算这些比率，使得给定核心的访问权限的比例大于访问权限的比率对于另一个核心，其响应性能高于给定核心; 并通知仲裁电路计算的访问权限比率。

14. 发明申请

US20110229901A1 METHODS FOR IDENTIFYING THE HABITATS OF INSECTS 有权
标题翻译：识别病人栖息地的方法
公开(公告)号：US20110229901A1
公开(公告)日：2011-09-22
申请号：US13120582
申请日：2009-09-17
申请人： Hiromasa Yamauchi
发明人： Hiromasa Yamauchi
IPC分类号： C12Q1/68 , C07H21/00 , G06F19/00
CPC分类号： C12Q1/6888 , C12Q1/6876 , C12Q2600/156 , C12Q2600/172
摘要： A method for preparing a criterion for identifying the habitat of insects of the same kind, comprising the steps of: (a) determining the nucleotide sequences of DNA of one or more insects from two or more habitats; (b) aligning the nucleotide sequences determined in said step (a); (c) eliminating sites consisting of one or more nucleotides conserved in all of the nucleotide sequences aligned in said step (b) from the nucleotide sequences; (d) defining all or a part of the sites remaining upon elimination in said step (c) as type-discriminating sites; (e) comparing nucleotides corresponding to each other in the type-discriminating sites obtained in said step (d) to classify completely identical type-discriminating sites as the same type and incompletely identical type-discriminating sites as one or more different types; and (f) determining the habitat of each type classified in said step (e) on the basis of the habitats of insects belonging to each type, thereby defining the type-discriminating site of each type as a criterion.
摘要翻译：一种制备用于鉴定同类昆虫栖息地的标准的方法，包括以下步骤：（a）从两个或多个栖息地确定一种或多种昆虫的DNA的核苷酸序列; （b）使在所述步骤（a）中确定的核苷酸序列对齐; （c）从核苷酸序列中消除由在所述步骤（b）中排列的所有核苷酸序列中保守的一个或多个核苷酸组成的位点; （d）将所述步骤（c）中消除的所有或部分剩余部位定义为类型鉴别场所; （e）比较在所述步骤（d）中获得的类型鉴别位点中彼此相对应的核苷酸，以将完全相同的类型鉴别位点分类为与一种或多种不同类型相同类型和不完全相同的类型鉴别位点; （f）根据属于每种类型的昆虫的栖息地确定在所述步骤（e）中分类的每种类型的栖息地，由此定义每种类型的种类鉴别位点作为标准。

15. 发明授权

US09110733B2 Multi-core processor system, arbiter circuit control method, and computer product 有权
标题翻译：多核处理器系统，仲裁电路控制方法和计算机产品
公开(公告)号：US09110733B2
公开(公告)日：2015-08-18
申请号：US13613634
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi
发明人： Koichiro Yamashita , Hiromasa Yamauchi
IPC分类号： G06F9/50 , G06F13/16
CPC分类号： G06F9/5083 , G06F9/5016 , G06F13/16 , G06F13/1605 , G06F13/1652
摘要： A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights.
摘要翻译：多核处理器系统包括多个核心; 由内核访问的共享内存; 以及仲裁电路，其仲裁由核心访问共享存储器的权限的争用。每个核心被配置为获取核心，测量到共享存储器的访问速度; 计算核心，基于测量的访问速度和核心访问理论速度的响应性能; 计算核心，并根据为每个核心计算的响应性能，访问共享内存的访问权限的比例，计算这些比率，使得给定核心的访问权限的比例大于访问权限的比率对于另一个核心，其响应性能高于给定核心; 并通知仲裁电路计算的访问权限比率。

16. 发明申请

US20130007763A1 GENERATING METHOD, SCHEDULING METHOD, COMPUTER PRODUCT, GENERATING APPARATUS, AND INFORMATION PROCESSING APPARATUS 审中-公开
标题翻译：产生方法，调度方法，计算机产品，生成装置和信息处理装置
公开(公告)号：US20130007763A1
公开(公告)日：2013-01-03
申请号：US13613972
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/4881 , G06F9/5083
摘要： A generating method is executed by a processor. The method includes executing simulation using a simulation model expressing a processor model, a memory model to which the processor model is accessible, and a load source that accesses the memory model according to an access contention rate, to obtain an index value for performance of the processor model, for each access contention rate; and saving to a memory area and as contention characteristics information, the index value for each access contention rate.
摘要翻译：生成方法由处理器执行。该方法包括使用表示处理器模型的模拟模型，可访问处理器模型的存储器模型以及根据接入争用速率访问存储器模型的负载源来执行仿真，以获得用于执行处理器型号，针对每个访问争用率; 并存储到存储区域和作为争用特征信息，每个访问争用率的索引值。

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