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11. 发明授权

US07664925B2 Arrangements having security protection 有权
标题翻译：有安全保护的安排
公开(公告)号：US07664925B2
公开(公告)日：2010-02-16
申请号：US12258685
申请日：2008-10-27
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F12/00
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.
摘要翻译：访问控制单元向访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落在在访问判断单元中登记的访问允许区域之一内，访问判断单元检查请求的地址是否落入在其中登记的访问许可区域，并且返回到访问控制单元的访问判断检查结果信号，该访问判断检查结果信号指示访问请求是否被遵从或拒绝，并且如果访问判断检查结果信号则访问控制单元允许访问内部总线表示要访问访问请求，否则拒绝访问请求。

12. 发明授权

US07917718B2 Arrangements having security protection 有权
标题翻译：有安全保护的安排
公开(公告)号：US07917718B2
公开(公告)日：2011-03-29
申请号：US12706285
申请日：2010-02-16
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F13/00
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： An external bus interface method including: receiving, via an access control unit, an access request conveyed through an external bus, and judging, via an access judging unit connected to the access control unit, whether the access request is to be honored or rejected, wherein upon receiving the access request, the access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit, an access judging check result signal indicating whether the access request is to be honored or rejected, and if the access judging check result signal indicates that the access request is to be rejected, the access control unit nullifies the access request.
摘要翻译：一种外部总线接口方法，包括：经由访问控制单元接收通过外部总线传送的访问请求，并且经由与所述访问控制单元连接的访问判断单元判断所述访问请求是否被履行或拒绝，其中，在接收到所述访问请求时，所述访问控制单元向所述访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落入在所述访问判断单元中登记的访问允许区域之一内，所述访问判断单元检查是否所请求的地址落在登记在其中的访问许可区域之一内，并返回到访问控制单元，指示是否要访问或拒绝访问请求的访问判断检查结果信号，以及访问判断检查结果信号是否指示访问请求将被拒绝，访问控制单元使访问请求无效。

13. 发明授权

US07444487B2 Arrangements having security protection 有权
标题翻译：有安全保护的安排
公开(公告)号：US07444487B2
公开(公告)日：2008-10-28
申请号：US11702538
申请日：2007-02-06
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F12/00
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.
摘要翻译：访问控制单元向访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落在在访问判断单元中登记的访问允许区域之一内，访问判断单元检查请求的地址是否落入在其中登记的访问许可区域，并且返回到访问控制单元的访问判断检查结果信号，该访问判断检查结果信号指示访问请求是否被遵从或拒绝，并且如果访问判断检查结果信号则访问控制单元允许访问内部总线表示要访问访问请求，否则拒绝访问请求。

14. 发明申请

US20070136543A1 Arrangements having security protection 有权
标题翻译：有安全保护的安排
公开(公告)号：US20070136543A1
公开(公告)日：2007-06-14
申请号：US11702538
申请日：2007-02-06
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F12/14 , G06F13/00 , G06F12/00
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.
摘要翻译：访问控制单元向访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落在在访问判断单元中登记的访问允许区域之一内，访问判断单元检查请求的地址是否落入在其中登记的访问许可区域，并且返回到访问控制单元的访问判断检查结果信号，该访问判断检查结果信号指示访问请求是否被遵从或拒绝，并且如果访问判断检查结果信号则访问控制单元允许访问内部总线表示要访问访问请求，否则拒绝访问请求。

15. 发明授权

US08483279B2 Moving image parallel processor having deblocking filters 有权
标题翻译：具有去块滤波器的运动图像并行处理器
公开(公告)号：US08483279B2
公开(公告)日：2013-07-09
申请号：US12819394
申请日：2010-06-21
申请人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
发明人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
IPC分类号： H04N7/12
CPC分类号： H04N19/86 , H04N19/423 , H04N19/436
摘要： A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.
摘要翻译：运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。第一和第二运动图像处理器分别包括第一和第二去块滤波器。与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

16. 发明申请

US20110096879A1 FILTER PROCESSING DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：滤波器处理器件和半导体器件
公开(公告)号：US20110096879A1
公开(公告)日：2011-04-28
申请号：US13002324
申请日：2009-06-26
申请人： Masakazu Ehama , Koji Hosogi
发明人： Masakazu Ehama , Koji Hosogi
IPC分类号： H04B1/10 , G06F17/10
CPC分类号： H03H17/0294 , H04N19/117 , H04N19/42 , H04N19/523 , H04N19/80
摘要： The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.
摘要翻译：本发明提供了一种用于在不需要执行分支处理的情况下改变滤波处理中的抽头数量的技术。一种滤波处理装置，包括：运算电路，进行滤波运算的运算处理; 内部寄存器，其保留在运算电路中进行算术处理的数据，并从运算电路接收运算结果的结果作为要被写回的数据; 以及数据生成器，其通过使用保持在内部寄存器中的数据来生成要馈送到运算电路的数据。此外，在滤波处理装置中，设置有能够根据施加到其上的抽头控制信号来控制滤波处理中的抽头数的抽头号控制电路。在这种配置中，通过使用抽头数控制电路来控制抽头数目不需要分支处理。

17. 发明授权

US08812572B2 Filter processing device and semiconductor device 有权
标题翻译：滤波处理装置及半导体装置
公开(公告)号：US08812572B2
公开(公告)日：2014-08-19
申请号：US13002324
申请日：2009-06-26
申请人： Masakazu Ehama , Koji Hosogi
发明人： Masakazu Ehama , Koji Hosogi
IPC分类号： G06F17/10
CPC分类号： H03H17/0294 , H04N19/117 , H04N19/42 , H04N19/523 , H04N19/80
摘要： The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.
摘要翻译：本发明提供了一种用于在不需要执行分支处理的情况下改变滤波处理中的抽头数量的技术。一种滤波处理装置，包括：运算电路，进行滤波运算的运算处理; 内部寄存器，其保留在运算电路中进行算术处理的数据，并从运算电路接收运算结果的结果作为要被写回的数据; 以及数据生成器，其通过使用保持在内部寄存器中的数据来生成要馈送到运算电路的数据。此外，在滤波处理装置中，设置有能够根据施加到其上的抽头控制信号来控制滤波处理中的抽头数的抽头号控制电路。在这种配置中，通过使用抽头数控制电路来控制抽头数目不需要分支处理。

18. 发明申请

US20100211623A1 FILTER PROCESSING MODULE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：过滤处理模块和半导体器件
公开(公告)号：US20100211623A1
公开(公告)日：2010-08-19
申请号：US12705898
申请日：2010-02-15
申请人： Yoshitaka HIRAMATSU , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki
发明人： Yoshitaka HIRAMATSU , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki
IPC分类号： G06F17/10 , G06F5/01
CPC分类号： G06F17/153 , G06T1/20 , H03H17/0202
摘要： The present invention is directed to improve efficiency of a filter processing on an image. A filter processing module includes a filter circuit and a control circuit. The filter circuit includes: a first register capable of storing data; a first arithmetic logic unit capable of executing a first filter processing on the basis of output data of the first register; a second register capable of storing a result of the arithmetic operation of the first arithmetic logic unit; and a second arithmetic logic unit capable of executing a second filter processing on the basis of output data of the second register. The control circuit adjusts the number of pieces of data which is input per cycle in the first register in accordance with the number of taps in the first filter processing, size of an execution result of the first filter processing, and the number of second arithmetic logic units, thereby promptly completing the first filter processing.
摘要翻译：本发明旨在提高对图像的滤波处理的效率。滤波器处理模块包括滤波电路和控制电路。滤波电路包括：能够存储数据的第一寄存器; 第一算术逻辑单元，其能够基于第一寄存器的输出数据执行第一滤波处理; 第二寄存器，其能够存储第一算术逻辑单元的算术运算结果; 以及能够基于第二寄存器的输出数据执行第二滤波处理的第二算术逻辑单元。控制电路根据第一滤波处理中的抽头数，第一滤波处理的执行结果的大小和第二算术逻辑的数量来调整在第一寄存器中每个周期输入的数据数单位，从而及时完成第一次过滤处理。

19. 发明授权

US09503728B2 Image processing device, decoding method, intra-frame decoder, method of decoding intra-frame and intra-frame encoder 有权
标题翻译：图像处理装置，解码方法，帧内解码器，帧内编码方式和帧内编码方式
公开(公告)号：US09503728B2
公开(公告)日：2016-11-22
申请号：US13144546
申请日：2009-01-15
申请人： Seiji Mochizuki , Yutaka Funabashi , Junichi Kimura , Masakazu Ehama
发明人： Seiji Mochizuki , Yutaka Funabashi , Junichi Kimura , Masakazu Ehama
IPC分类号： H04N7/32 , H04N19/11 , H04N19/61 , H04N19/593 , H04N19/44 , H04N19/583
CPC分类号： H04N19/11 , H04N19/44 , H04N19/583 , H04N19/593 , H04N19/61
摘要： Adopted is a decoder, in which on condition that a prediction block shown by vector information extracted from a data stream, and a decode-target block have an overlap where respective pixels overlay each other, pixel information of an already-decoded portion at a distance of an integer multiple of a vector provided by the vector information from the overlap is made a prediction signal instead of the overlap, and the prediction signal is added to difference image data taken from the data stream to generate reproduction image data. The decoder is adopted for an intra-frame decoder, a local decoder of an encoder, and the like. According to a fundamental rule concerning a repetitive pattern of an image, a pixel at a distance of an integer multiple is a like pixel, and therefore the process of decoding can be performed efficiently.
摘要翻译：采用的是一种解码器，其中在从数据流提取的向量信息所示的预测块和解码目标块具有彼此重叠的重叠的条件下，已经解码的部分的像素信息在距离将来自重叠的向量信息提供的向量的整数倍的整数倍作为预测信号，而不是重叠，并将预测信号加到从数据流中取出的差分图像数据，以产生再现图像数据。解码器用于帧内解码器，编码器的本地解码器等。根据关于图像的重复图案的基本规则，整数倍的距离处的像素是相似的像素，因此可以有效地执行解码处理。

20. 发明授权

US08958479B2 Compressed dynamic image encoding device, compressed dynamic image decoding device, compressed dynamic image encoding method and compressed dynamic image decoding method 有权
标题翻译：压缩动态图像编码装置，压缩动态图像解码装置，压缩动态图像编码方法和压缩动态图像解码方法
公开(公告)号：US08958479B2
公开(公告)日：2015-02-17
申请号：US13203727
申请日：2009-03-04
申请人： Seiji Mochizuki , Junichi Kimura , Masakazu Ehama
发明人： Seiji Mochizuki , Junichi Kimura , Masakazu Ehama
IPC分类号： H04N7/26 , H04N19/583 , H04N19/136 , H04N19/563 , H04N19/85 , H04N19/61
CPC分类号： H04N19/85 , H04N19/136 , H04N19/51 , H04N19/563 , H04N19/61
摘要： A compressed dynamic image encoding device is provided, in which a motion vector is generated by searching a reference image for an image area most similar to an image area of a video input signal; a motion-compensated reference image is generated from the motion vector and the reference image; a prediction residual is generated, by subtracting the motion-compensated reference image from the video input signal; the reference image is generated, by adding the motion-compensated reference image and the result of processing performed to the prediction residual; and an encoded video output signal is generated by the processing performed to the prediction residual. The reference image comprises on-screen reference images, located inside a video display screen, and an off-screen reference image located outside the video display screen, and the off-screen reference image is generated based on the positional relationship of plural similar reference images of the on-screen reference images.
摘要翻译：提供了一种压缩动态图像编码装置，其中通过搜索参考图像来产生与图像输入信号的图像区域最相似的图像区域来生成运动矢量; 从运动矢量和参考图像生成运动补偿参考图像; 通过从视频输入信号中减去运动补偿参考图像来产生预测残差; 通过将运动补偿参考图像和对预测残差执行的处理结果相加来生成参考图像; 并且通过对预测残差执行的处理来生成编码视频输出信号。参考图像包括位于视频显示屏内的屏幕参考图像和位于视频显示屏外部的离屏参考图像，并且基于多个相似参考图像的位置关系生成离屏参考图像的屏幕参考图像。

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