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11. 发明授权

US06944696B2 Data processing processor 失效
标题翻译：数据处理处理器
公开(公告)号：US06944696B2
公开(公告)日：2005-09-13
申请号：US10673851
申请日：2003-09-30
申请人： Hiroshi Yamada , Toyokazu Hori , Masaru Hase , Tetsuya Yamato , Norihiko Sugita
发明人： Hiroshi Yamada , Toyokazu Hori , Masaru Hase , Tetsuya Yamato , Norihiko Sugita
IPC分类号： G06F12/00 , G06F13/18 , G06F13/362 , G06F13/36
CPC分类号： G06F13/3625
摘要： A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
摘要翻译：用于图像处理处理器的总线仲裁装置是可操作的，使得当具有高实时处理操作的必要性的信道发布总线使用请求时，总线使用许可不被给予具有低真实性的另一信道时间处理操作。数据的总线仲裁器包括：相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器，以及用于实时处理操作的必要性低的信道的寄存器。大于定时器最大值的值被设置为寄存器的值。在总线仲裁中，将寄存器的值与定时器的值进行比较，然后将总线使用许可赋予具有较小值的通道。

12. 发明授权

US07026188B2 Electronic device and method for manufacturing the same 失效
标题翻译：电子设备及其制造方法
公开(公告)号：US07026188B2
公开(公告)日：2006-04-11
申请号：US10481463
申请日：2002-03-08
申请人： Kazuyuki Taguchi , Norihiko Sugita , Hideki Tanaka
发明人： Kazuyuki Taguchi , Norihiko Sugita , Hideki Tanaka
IPC分类号： H01L21/50 , H05K3/32
CPC分类号： H01L24/06 , H01L21/563 , H01L23/13 , H01L23/49816 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/06136 , H01L2224/1134 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2224/83192 , H01L2224/92125 , H01L2225/1005 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3511 , H05K1/181 , H05K3/323 , H05K3/3436 , H05K3/3463 , H05K2201/10674 , H05K2201/10734 , H05K2203/047 , Y02P70/611 , H01L2224/13099 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2924/00015 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/05552 , H01L2224/81805 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of an electronic device comprises the steps of: preparing a printed wiring board having a first region and a second region which differ from each other over one main surface thereof, a first electronic component having a plurality of first projection electrodes over one main surface thereof, and a second electronic component having a plurality of second projection electrodes which have a melting point higher than a melting point of the first projection electrodes over one main surface thereof; mounting the first electronic component on the first region of one main surface of the printed wiring board by melting the plurality of first projection electrodes; and mounting the second electronic component on the second region of one main surface of the printed wiring board by compression-bonding the second electronic component while heating in a state that an adhesive resin is interposed between the second region of one main surface of the printed wiring board and one main surface of the second electronic component wherein the step of mounting the second electronic component is performed before the step of mounting the first electronic component.
摘要翻译：电子设备的制造方法包括以下步骤：制备具有在其一个主表面上彼此不同的第一区域和第二区域的印刷布线板，第一电子部件，其具有在一个主体上的多个第一突出电极以及具有多个第二突出电极的第二电子部件，该第二突出电极的熔点高于其一个主表面上的第一突起电极的熔点; 通过熔化多个第一突起电极将第一电子部件安装在印刷电路板的一个主表面的第一区域上; 以及在印刷布线的一个主表面的第二区域之间插入粘合剂树脂的状态下，通过压缩第二电子部件的同时将第二电子部件安装在印刷线路板的一个主表面的第二区域上板和一个主表面，其中在安装第一电子部件的步骤之前执行安装第二电子部件的步骤。

13. 发明授权

US06658511B2 Data processing processor 有权
标题翻译：数据处理处理器
公开(公告)号：US06658511B2
公开(公告)日：2003-12-02
申请号：US09745928
申请日：2000-12-26
申请人： Hiroshi Yamada , Toyokazu Hori , Masaru Hase , Tetsuya Yamato , Norihiko Sugita
发明人： Hiroshi Yamada , Toyokazu Hori , Masaru Hase , Tetsuya Yamato , Norihiko Sugita
IPC分类号： G06F1300
CPC分类号： G06F13/3625
摘要： A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
摘要翻译：用于图像处理处理器的总线仲裁装置是可操作的，使得当具有高实时处理操作的必要性的信道发布总线使用请求时，总线使用许可不被给予具有低真实性的另一信道时间处理操作。数据的总线仲裁器包括：相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器，以及用于实时处理操作的必要性低的信道的寄存器。大于定时器最大值的值被设置为寄存器的值。在总线仲裁中，将寄存器的值与定时器的值进行比较，然后将总线使用许可赋予具有较小值的通道。

14. 发明授权

US07982217B2 Semiconductor device and its test method 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US07982217B2
公开(公告)日：2011-07-19
申请号：US12153746
申请日：2008-05-23
申请人： Norihiko Sugita , Tetsuo Ishiguro , Naoki Yashiki
发明人： Norihiko Sugita , Tetsuo Ishiguro , Naoki Yashiki
IPC分类号： H01L21/66
CPC分类号： G01R31/318513 , G01R31/31926 , H01L2224/73204 , H01L2224/83192
摘要： A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.
摘要翻译：包括接收从第一半导体芯片给出的操作指令并输出与其对应的信号的操作的第二半导体芯片安装在安装装置上。用于互连第一和第二半导体芯片的内部布线以及分别连接到内部布线的外部端子设置在安装装置中以构成多芯片模块。此外，在模块内部设置用于使从第一半导体芯片到第二半导体芯片的操作指令无效化的信号路径。

15. 发明申请

US20050169033A1 Semiconductor module 审中-公开
标题翻译：半导体模块
公开(公告)号：US20050169033A1
公开(公告)日：2005-08-04
申请号：US11095571
申请日：2005-04-01
申请人： Norihiko Sugita , Takafumi Kikuchi , Koichi Miyashita , Hikaru Ikegami
发明人： Norihiko Sugita , Takafumi Kikuchi , Koichi Miyashita , Hikaru Ikegami
IPC分类号： G11C5/00 , G11C5/06 , H05K1/02 , H05K1/14
CPC分类号： G11C5/06 , G11C5/005 , G11C5/04 , H01L23/50 , H01L23/552 , H01L25/16 , H01L2224/16225 , H01L2924/3011 , H05K1/0216 , H05K1/141
摘要： A high speed operating circuit such as a data processor chip and memory chips constituting an electronic circuit is mounted to a multilayer wiring substrate in the state of a bare chip, and is set to a multichip module. This multichip module is mounted to a wiring substrate constituting the electronic circuit. In the multichip module, buffer circuits are inserted into a module internal bus commonly connected to the data processor chip and the memory chips. The buffer circuits are set to an address output buffer, a control signal output buffer and a data input/output buffer set to a high impedance state in accordance with an operating selection of the memory chips. When high frequency noise resisting characteristics are strengthened by the multilayer wiring substrate and the data processor chip gets access to the memory chips, an external noise tends to flow into a memory through the module internal bus connected to the data processor chip and the memory chips. However, the buffer circuits restrain the flow-in of such an external noise and prevent memory data from being broken by the high frequency noise during a memory access operation.
摘要翻译：构成电子电路的数据处理器芯片和存储器芯片等高速运算电路以裸芯片的状态安装在多层布线基板上，设置于多芯片模块。该多芯片模块安装到构成电子电路的布线基板。在多芯片模块中，缓冲电路被插入到共同连接到数据处理器芯片和存储器芯片的模块内部总线中。根据存储器芯片的操作选择，将缓冲电路设置为地址输出缓冲器，控制信号输出缓冲器和设置为高阻抗状态的数据输入/输出缓冲器。当通过多层布线基板和数据处理器芯片获得对存储器芯片的访问来增强高频抗噪声特性时，通过连接到数据处理器芯片和存储器芯片的模块内部总线，外部噪声趋于流入存储器。然而，缓冲电路抑制这种外部噪声的流入，并且在存储器访问操作期间防止存储器数据被高频噪声破坏。

16. 发明申请

US20050099199A1 Semiconductor device and its test method 审中-公开
标题翻译：半导体器件及其测试方法
公开(公告)号：US20050099199A1
公开(公告)日：2005-05-12
申请号：US10468794
申请日：2001-12-26
申请人： Norihiko Sugita , Tetsuo Ishiguro , Naoki Yashiki
发明人： Norihiko Sugita , Tetsuo Ishiguro , Naoki Yashiki
IPC分类号： H01L21/822 , G01R31/26 , G01R31/319 , H01L21/66 , G01R31/02
CPC分类号： G01R31/318513 , G01R31/31926 , H01L2224/73204 , H01L2224/83192
摘要： A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.
摘要翻译：包括接收从第一半导体芯片给出的操作指令并输出与其对应的信号的操作的第二半导体芯片安装在安装装置上。用于互连第一和第二半导体芯片的内部布线以及分别连接到内部布线的外部端子设置在安装装置中以构成多芯片模块。此外，在模块内部设置用于使从第一半导体芯片到第二半导体芯片的操作指令无效化的信号路径。

17. 发明授权

US06815746B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06815746B2
公开(公告)日：2004-11-09
申请号：US10268699
申请日：2002-10-11
申请人： Makoto Suzuki , Takafumi Kikuchi , Norihiko Sugita , Seiichi Shirakawa
发明人： Makoto Suzuki , Takafumi Kikuchi , Norihiko Sugita , Seiichi Shirakawa
IPC分类号： H01L27108
CPC分类号： H01L24/06 , B82Y10/00 , G11C11/005 , G11C2207/105 , H01L21/561 , H01L23/50 , H01L23/5386 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a small-sized and inexpensive semiconductor device wherein a synchronous dynamic random access memory and a flash memory are built in a single encapsulater. A flash memory chip and a synchronous dynamic random access memory chip (SDRAM chip) are fixed to a main surface of a wiring board in a parallel state, and another SDRAM chip is fixed onto the flash memory chip. Electrodes for the respective semiconductor chips are respectively exposed and these electrodes are connected to their corresponding electrodes of the wiring board. An encapsulater formed of an insulating resin is formed on the main surface side of the wiring board so as to cover wires. Since the encapsulater is formed by cutting a block encapsulater formed by block molding by dicing, the side faces of the encapsulater result in cut surfaces. Bump electrodes are provided on the back surface of the wiring board in an array fashion.
摘要翻译：本发明提供了一种小型且便宜的半导体器件，其中同步动态随机存取存储器和闪速存储器被构建在单个封装器中。闪存芯片和同步动态随机存取存储器芯片（SDRAM芯片）以并行状态固定到布线板的主表面，另一个SDRAM芯片固定到闪存芯片上。分别露出用于各个半导体芯片的电极，并且这些电极连接到其对应的布线板的电极。在布线板的主表面侧形成由绝缘树脂构成的封装体，以覆盖电线。由于密封剂是通过切割由块状模塑形成的块状密封剂形成的，因此密封剂的侧面产生切割面。凸起电极以阵列方式设置在布线板的背面上。

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