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11. 发明申请

US20130168793A1 AVALANCHE PHOTODIODE 有权
标题翻译： AVALANCHE光电
公开(公告)号：US20130168793A1
公开(公告)日：2013-07-04
申请号：US13819559
申请日：2011-09-01
申请人： Tadao Ishibashi , Seigo Ando , Masahiro Nada , Yoshifumi Muramoto , Haruki Yokoyama
发明人： Tadao Ishibashi , Seigo Ando , Masahiro Nada , Yoshifumi Muramoto , Haruki Yokoyama
IPC分类号： H01L31/02
CPC分类号： H01L31/02002 , H01L31/022416 , H01L31/03046 , H01L31/035281 , H01L31/1075 , Y02E10/544
摘要： An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outer circumference of the first mesa and encircling an outer circumference of the second mesa, and prevents the encircling portion of the p-type electric field control layer from being depleted when bias is applied.
摘要翻译： APD设置有半绝缘基板，第一台面具有第一层叠结构，其中p型电极层，p型光吸收层，具有低杂质浓度的光吸收层，带隙倾斜层叠，p型电场控制层，雪崩乘法器层，n型电场控制层和具有低杂质浓度的电子传输层依次层叠在半绝缘基板的表面上，第二台面，其具有从层叠方向观察时设置在第一台面的外周的外周，并且具有第二层叠结构，其中n型电极缓冲层和n型电极层依次层叠在电子转移层侧的表面和相对于p型电场控制层设置在第二台面侧的层的耗尽控制区域，形成在环状端口 n设置在第一台面的外周内并且围绕第二台面的外周，并且在施加偏压时防止p型电场控制层的环绕部分耗尽。

12. 发明授权

US08401344B2 Semiconductor optical modulator and optical modulating apparatus 有权
标题翻译：半导体光调制器和光调制装置
公开(公告)号：US08401344B2
公开(公告)日：2013-03-19
申请号：US12811565
申请日：2008-12-26
申请人： Tadao Ishibashi , Kazuhiro Maruyama , Kenji Kobayashi , Tomoyuki Akeyoshi , Nobuhiro Kikuchi , Ken Tsuzuki , Mitsuteru Ishikawa
发明人： Tadao Ishibashi , Kazuhiro Maruyama , Kenji Kobayashi , Tomoyuki Akeyoshi , Nobuhiro Kikuchi , Ken Tsuzuki , Mitsuteru Ishikawa
IPC分类号： G02F1/035
CPC分类号： G02F1/025 , G02F2201/07
摘要： A semiconductor optical modulator that includes a first semiconductor optical waveguide having a laminated structure including a core layer, a first clad layer, a second clad layer, and a barrier layer, the first clad layer and the second clad layer being disposed below and above the core layer, the barrier layer being inserted between the second clad layer and the core layer; a second semiconductor optical waveguide having a laminated structure in which the second clad layer has a p-type semiconductor penetrating locally through a n-type semiconductor in a laminated direction in the laminated structure of the first semiconductor optical waveguide; a first electrode connected to the first clad layer of the first semiconductor optical waveguide; and a second electrode electrically connecting the second clad layer of the first semiconductor optical waveguide and the p-type semiconductor of the second clad layer of the second semiconductor optical waveguide.
摘要翻译：一种半导体光调制器，包括具有芯层，第一覆层，第二覆层和阻挡层的叠层结构的第一半导体光波导，第一覆层和第二覆层设置在第一半导体光波导的下方和上方所述阻挡层插入在所述第二覆盖层和所述芯层之间; 具有层叠结构的第二半导体光波导，其中所述第二包层具有在所述第一半导体光波导的层叠结构中在层叠方向上局部穿透n型半导体的p型半导体; 连接到第一半导体光波导的第一包层的第一电极; 以及第二电极，电连接第一半导体光波导的第二包层和第二半导体光波导的第二包层的p型半导体。

13. 发明授权

US07787736B2 Semiconductor optoelectronic waveguide 失效
标题翻译：半导体光电波导
公开(公告)号：US07787736B2
公开(公告)日：2010-08-31
申请号：US12219061
申请日：2008-07-15
申请人： Tadao Ishibashi , Seigo Ando , Ken Tsuzuki
发明人： Tadao Ishibashi , Seigo Ando , Ken Tsuzuki
IPC分类号： G02B6/10
CPC分类号： G02F1/01708 , B82Y20/00
摘要： The present invention relates to a semiconductor optoelectronic waveguide having a nin-type hetero structure which is able to stably operate an optical modulator. On the upper and lower surfaces of the core layer determined for the structure so that electro-optical effects are effectively exerted at an operating light wavelength and are provided with intermediate clad layers having a band gap which is greater than that of the core layer 11. Respectively on the upper and the lower surface of the intermediate clad layer are provided the clad layers having the band gap which is greater than those of the intermediate clad layers. On the upper surface of the clad layer are sequentially laminated a p-type layer and an n-type layer. In the applied voltage range used under an operating state, a whole region of the p-type layer and a part or a whole region of the n-type layer are depleted.
摘要翻译：本发明涉及能够稳定地操作光调制器的具有n型异质结构的半导体光电波导。在对于结构确定的芯层的上表面和下表面上，使得电光效应在工作光波长下有效地施加，并且设置有具有比芯层11的带隙大的带隙的中间包层。在中间包层的上表面和下表面上分别设置具有大于中间包层的带隙的包覆层。在包覆层的上表面依次层叠p型层和n型层。在工作状态下使用的施加电压范围内，p型层的整个区域和n型层的一部分或全部区域耗尽。

14. 发明申请

US20070200141A1 Avalanche Photodiode 有权
标题翻译：雪崩光电二极管
公开(公告)号：US20070200141A1
公开(公告)日：2007-08-30
申请号：US10587818
申请日：2005-02-03
申请人： Tadao Ishibashi , Seigo Ando , Yukihiro Hirota
发明人： Tadao Ishibashi , Seigo Ando , Yukihiro Hirota
IPC分类号： H01L31/00
CPC分类号： H01L31/1075
摘要： An ultra high speed APD capable of realizing reduction in an operating voltage and quantum efficiency enhancement at the same time is provided. Under operating conditions APD, a doping concentration distribution of each light absorbing layer is determined so that a p-type light absorbing layer (16) maintains a p-type neutrality except a part thereof, and a low concentration light absorbing layer (15) is depleted. Moreover, a ratio between a layer thickness WAN of the p-type light absorbing layer (16) and a layer thickness WAD of the low concentration light absorbing layer (15) is determined so that WAD>0.3 μm and a delay time of an element response accompanying a transit of carriers generated in the light absorbing layer by light absorption takes on a local minimum under a condition that a layer thickness WA (=WAN+WAD) of the light absorbing layer is constant.
摘要翻译：提供能够同时实现工作电压降低和量子效率提高的超高速APD。在操作条件APD下，确定每个光吸收层的掺杂浓度分布，使得p型光吸收层（16）除了其一部分之外保持p型中性，并且低浓度光吸收层（15）为耗尽此外，p型光吸收层（16）的层厚度W AN AN与低浓度光吸收层（15）的层厚度W SUB / SUB之比），使得在光吸收层中通过光吸收产生的载流子的转移伴随的元素响应的延迟时间在层的一个条件下成为局部最小值光吸收层的厚度W A（= W AN AN + W AD AD）是恒定的。

15. 发明授权

US4508786A Polyolefin resin composition 失效
标题翻译：聚烯烃树脂组合物
公开(公告)号：US4508786A
公开(公告)日：1985-04-02
申请号：US625951
申请日：1984-06-29
申请人： Tadao Ishibashi , Youichi Kugimiya
发明人： Tadao Ishibashi , Youichi Kugimiya
IPC分类号： C08L23/00 , B32B15/085 , C08K3/34 , C08L7/00 , C08L21/00 , C08L23/06 , C08L23/14 , C08L101/00 , C25D5/56 , B32B5/00 , C23C15/00
CPC分类号： C08L23/142 , C08K3/34 , C08L23/06 , Y10T428/31692
摘要： A polyolefin resin composition for metallized films, having superior high-impact properties and heat-sealability and also superior printability and adhesive properties of metallized surface and further a good taken-up figure of rolled film is provided, which composition is obtained by blending a crystalline propylene-.alpha.-olefin copolymer containing 70% by weight or more of propylene component and having a crystalline m.p. of 150.degree. C. or lower, with a high density polyethylene having a density of 0.940 g/cm.sup.3 or higher, in blending ratios of 96 to 80% by weight of the copolymer and 4 to 20% by weight of the polyethylene, the ratio of the melt flow rate of the polyethylene to that of the copolymer being .gtoreq.0.7.
摘要翻译：一种用于金属化膜的聚烯烃树脂组合物，具有优异的高冲击性和热封性，并且还具有优异的印刷性和金属化表面的粘合性，并且还提供了良好的轧制膜卷取，该组合物通过将结晶含有70重量％以上丙烯成分并具有结晶mp的丙烯-α-烯烃共聚物与密度为0.940g / cm 3以上的高密度聚乙烯，共聚物的共聚比例为96〜80重量％，聚乙烯为4〜20重量％，比例为150℃以下的聚乙烯的熔体流动速率与共聚物的熔体流动速率> 0.7。

16. 发明授权

US08754445B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08754445B2
公开(公告)日：2014-06-17
申请号：US13981050
申请日：2012-01-20
申请人： Tadao Ishibashi , Seigo Ando , Yoshifumi Muramoto , Toshihide Yoshimatsu , Haruki Yokoyama
发明人： Tadao Ishibashi , Seigo Ando , Yoshifumi Muramoto , Toshihide Yoshimatsu , Haruki Yokoyama
IPC分类号： H01L31/107
CPC分类号： H01L29/0615 , G02F1/025 , G02F2001/0157 , H01L29/0692 , H01L29/0821 , H01L29/205 , H01L29/41708 , H01L29/42304 , H01L29/7371 , H01L31/03046 , H01L31/035281 , H01L31/105 , Y02E10/544
摘要： A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.
摘要翻译：产生通常不需要用于器件操作的电位电平差的层被积极地插入到器件结构中。电位差具有这样的功能：即使具有小的带隙的半导体暴露在台面侧表面上，也能够抑制该部分的电位下降量，并且能够减少不利于器件操作的漏电流。对于异质结双极晶体管，光电二极管，电吸收调制器等，通常可以获得这种效果。在光电二极管中，由于泄漏电流被减轻，所以能够减小器件尺寸，除了随着串联电阻的降低而提高工作速度之外，还可以将器件密集地排列成阵列。

17. 发明授权

US08575650B2 Avalanche photodiode 有权
标题翻译：雪崩光电二极管
公开(公告)号：US08575650B2
公开(公告)日：2013-11-05
申请号：US13133990
申请日：2009-12-11
申请人： Tadao Ishibashi , Seigo Ando , Yoshifumi Muramoto , Fumito Nakajima , Haruki Yokoyama
发明人： Tadao Ishibashi , Seigo Ando , Yoshifumi Muramoto , Fumito Nakajima , Haruki Yokoyama
IPC分类号： H01L31/107
CPC分类号： H01L31/1075
摘要： An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape.
摘要翻译：具有嵌入式n电极结构的电子注入APD，其中可以抑制边缘击穿而不以高精度控制嵌入式n电极结构的n型区域的掺杂分布。包括具有低电离速率的缓冲层的APD插入在n电极连接层和雪崩倍增层之间。具体地，APD是电子注入APD，其中n电极层，n电极连接层，缓冲层，雪崩倍增层，电场控制层，带隙梯度层，低浓度光吸收层 p型光吸收层和ap电极层依次层叠，并且至少包含低浓度光吸收层和p型光吸收层的光吸收部形成台面形状。

18. 发明申请

US20050001239A1 Photodiode 有权
标题翻译：光电二极管
公开(公告)号：US20050001239A1
公开(公告)日：2005-01-06
申请号：US10497490
申请日：2002-12-03
申请人： Tadao Ishibashi , Yukihiro Hirota , Yoshifumi Muramoto
发明人： Tadao Ishibashi , Yukihiro Hirota , Yoshifumi Muramoto
IPC分类号： H01L31/10 , H01L31/101 , H01L31/105 , H01L27/10
CPC分类号： H01L31/105 , H01L31/101
摘要： A photodiode has an optical absorption layer composed of a depleted first semiconductor optical absorption layer with a layer width WD and a p-type neutral second semiconductor optical absorption layer with a layer width WA. The ratio between WA and WD is set such that the total carrier transit time τtot becomes minimum in the optical absorption layer. The photodiode can further include a depleted semiconductor optical transmission layer with a bandgap greater than that of the first semiconductor optical absorption layer, between the first semiconductor optical absorption layer and an n-type semiconductor electrode layer.
摘要翻译：光电二极管具有由具有层宽度WD的贫化的第一半导体光吸收层和具有层宽度WA的p型中性第二半导体光吸收层构成的光吸收层。 WA和WD之间的比率被设定为使得在光吸收层中总载流子传播时间tautot变得最小。光电二极管还可以包括在第一半导体光吸收层和n型半导体电极层之间具有比第一半导体光吸收层的带隙大的带隙的耗尽的半导体光透射层。

19. 发明授权

US5557117A Heterojunction bipolar transistor and integrated circuit device using the same 失效
标题翻译：异质结双极晶体管和使用其的集成电路器件
公开(公告)号：US5557117A
公开(公告)日：1996-09-17
申请号：US241189
申请日：1994-05-11
申请人： Yutaka Matsuoka , Eiichi Sano , Kenji Kurishima , Hiroki Nakajima , Tadao Ishibashi
发明人： Yutaka Matsuoka , Eiichi Sano , Kenji Kurishima , Hiroki Nakajima , Tadao Ishibashi
IPC分类号： H01L29/205 , H01L21/331 , H01L27/144 , H01L29/08 , H01L29/73 , H01L29/737 , H01L31/10 , H01L31/11 , H01L31/0328
CPC分类号： H01L29/7371 , H01L27/1443 , H01L29/0821 , H01L31/1105
摘要： A heterojunction bipolar transistor includes a collector contact layer constituted by a high-concentration first semiconductor layer of a first conductivity type formed on a semiconductor substrate, a collector region stacked on the collector contact layer, a base layer constituted by a fifth semiconductor layer of a second conductivity type formed on the collector region, and an emitter layer constituted by a semiconductor layer of the first conductivity type formed on the base layer. The collector region is constituted by a second semiconductor layer, a third semiconductor layer of the second conductivity type having an impurity concentration higher than that of the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type having a band gap energy higher than that of each of the first and second semiconductor layers and an impurity concentration higher than that of the second semiconductor layer, and the fourth semiconductor layer and lower than that of the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer are sequentially formed on the collector contact layer in an order named.
摘要翻译：异质结双极晶体管包括由形成在半导体衬底上的第一导电类型的高浓度第一半导体层，堆叠在集电极接触层上的集电极区域构成的集电极接触层，由第五半导体层形成在集电极区域上的第二导电类型，以及由形成在基极层上的由第一导电类型的半导体层构成的发射极层。集电极区域由第二半导体层，具有比第二半导体层的杂质浓度高的第二导电类型的第三半导体层构成，第一导电类型的第四半导体层的带隙能量高于第一半导体层和第二半导体层的第一半导体层和第二半导体层的杂质浓度高于第二半导体层，第四半导体层的第一半导体层和第二半导体层的杂质浓度比第一半导体层的厚度低在收集器接触层上形成一个命名的顺序。

20. 发明授权

US5019890A Heterojunction bipolar transistor 失效
公开(公告)号：US5019890A
公开(公告)日：1991-05-28
申请号：US587451
申请日：1990-09-14
申请人： Tadao Ishibashi , Yoshiki Yamauchi
发明人： Tadao Ishibashi , Yoshiki Yamauchi
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/205 , H01L29/36 , H01L29/737
CPC分类号： H01L29/36 , H01L29/0821 , H01L29/7371
摘要： A heterojunction bipolar transistor includes an emitter layer of a first conductivity type, a base layer of a second conductivity type adjacent to the emitter layer, a collector buffer layer of the first conductivity type, and a collector layer arranged between the collector buffer layer and the base layer. The collector layer includes a first collector layer formed at the side of the base layer and a second collector layer arranged at the side of the collector buffer layer. The first collector layer is a semiconductor layer having an impurity concentration lower than that of the base layer. The second collector layer is a semiconductor layer of the second conductivity type having an impurity concentration higher than that of the first collector layer.

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