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11. 发明专利

JPH0560200B2 失效
公开(公告)号：JPH0560200B2
公开(公告)日：1993-09-01
申请号：JP1721186
申请日：1986-01-29
申请人： TOSHIBA KK , TOSHIBA MICRO ELECTRONICS
发明人： TANAKA SUMIO , ATSUMI SHIGERU , OOTSUKA NOBUAKI , KAMEI TAKASHI
IPC分类号： H01L27/10 , G11C16/06 , G11C17/00 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792 , H03K19/0185

12. 发明专利

JPH0324070B2 失效
公开(公告)号：JPH0324070B2
公开(公告)日：1991-04-02
申请号：JP4375186
申请日：1986-02-28
申请人： TOSHIBA KK , TOSHIBA MAIKURO EREKUTORONIKUSU KK
发明人： ATSUMI SHIGERU , SAITO SHINJI , TANAKA SUMIO , OOTSUKA NOBUAKI , YOSHIKAWA KUNYOSHI , KAMEI TAKASHI
IPC分类号： H01L21/8234 , G11C11/419 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/788 , H01L29/792

13. 发明专利

JPS60207383A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60207383A
公开(公告)日：1985-10-18
申请号：JP6368684
申请日：1984-03-31
申请人： TOSHIBA KK
发明人： TANAKA SUMIO , ATSUMI SHIGERU , TOZAWA CHIKASUMI , TSUSHIMA TOSHIKI , OKUDA TAIZOU , ASANO MASAMICHI
IPC分类号： H03F1/52 , G11C5/14 , G11C7/00 , G11C7/24 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/73 , H01L29/78 , H01L29/788 , H01L29/792 , H02H7/20 , H03F1/42
摘要： PURPOSE:To improve surge withstanding voltage by mounting a protective transistor introducing charges generated by applying surge voltage to a grounding point between a power supply terminal for a circuit constituted by an MOS transistor having LDD structure and the grounding point. CONSTITUTION:When surge voltage is applied to a high-voltage power supply terminal 19, an avalanche breakdown is generated on the interface B between the surface of a semiconductor substrate 11 and an N type impurity region 13, and electron-hole pairs are produced. Electrons are absorbed to the drain D side and holes flow in the direction of the substrate, substrate currents are generated, the P type semiconductor substrate 11 in the vicinity of a sources is biassed in the forward direction, and a parasitic bipolar transistor QB using an N type impurity region 122 as a collector, an N type impurity region 121 as an emitter and the P type semiconductor substrate 11 as a base is brought to an ON state. The source S is grounded, and surge voltage applied to the voltage supply terminal 19 is discharged rapidly. The surge voltage of an LDD type MOS transistor is improved.

14. 发明专利

JPS60159505A PULSE COMBUSTION BURNER 失效
公开(公告)号：JPS60159505A
公开(公告)日：1985-08-21
申请号：JP1261684
申请日：1984-01-26
申请人： TOSHIBA KK
发明人： TANAKA SUMIO
IPC分类号： F23C15/00
摘要： PURPOSE:To make it possible to freely vary the ability of the title burner while maintaining its stable combustion by providing in a gaseous fuel supply passage flow varying means varying the flow quantity of a gaseous fuel introduced into a combustion chamber. CONSTITUTION:A gas proportional control valve 15 proportionally varying a flow passage area by opening or closing the opening of a port by receiving a signal is interposed on a gaseous fuel supply passage 7b on the upstream side of a cushion tank 13. A combustion quantity adjusting dial 16 for adjusting the combustion quantity is connected to a signal input part of the gas proportional control valve 15 through an opening control circuit 17, and the proportional control valve 15 is driven by an opening degree control circuit 17 so that the combustion quantity corresponds to that set by the combustion quantity adjusting dial 16. That is, it is possible to vary the flow quantity of the gaseous fuel introduced into the combustion chamber 1 as an operating part.

15. 发明专利

JPS60140598A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPS60140598A
公开(公告)日：1985-07-25
申请号：JP25059383
申请日：1983-12-28
申请人： TOSHIBA KK
发明人： SAITOU SHINJI , TANAKA SUMIO , ATSUMI SHIGERU
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To allow high speed and reduction of current consumption by supplying a switching power source which becomes a voltage supply power source electric potential VCC at the time of reading and a writing power source electric potential VPP with high electric potential at the time of writing to a NAND circuit and a MOS inverter. CONSTITUTION:Since a switching power source VPP*=VCC is set at the time of reading, the output of a NAND circuit 10 is at L level and the output of an MOS inverter 20 becomes H level when all decode signals RD1-RDn is at H level. Since the write switching power source VPP* is set to the VPP electric potential, the output of the NAND circuit becomes L when all decode signals RD1-RDn is at H level, and the output becomes H when either one is at L level. Since a PGM signal is at L level and the output of an inverter 8 is at H level, the electric potential of the output L of the NAND circuit 10 has no change comparing with the electric potential at the time of reading, the switching speed is increased and the transitional current consumption becomes smaller.

16. 发明专利

JPS60101796A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS60101796A
公开(公告)日：1985-06-05
申请号：JP20937883
申请日：1983-11-08
申请人： TOSHIBA KK
发明人： SAITOU SHINJI , TANAKA SUMIO
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To perform fast writing operation and increase the amount of written information by using an internal write-in voltage higher than an external write- in voltage as the power source for a row decoder, and also using a lower internal write-in voltage as the power source for a column decoder. CONSTITUTION:A charge pump type boosting circuit consists of a ring oscillator 11, driver circuit 6d, capacitance 12, and intrinsic type n channel FET13. A voltage higher than the voltage at an external write-in terminal VPP is obtained at the output B of this boosting circuit and applied to the row driver 4 as an internal power source VPP'1 and also inputted to a switching circuit 1 which drives the column decoder. The output of the switching circuit 1 is used as an internal power source VPP'2 to obtain the voltage as high as the voltage at the terminal VPP during writing operation. Further, the internal power source VPP'1 is held at the same voltage with the power source VCC through a depletion type n channel FET14 during reading operation.

17. 发明专利

JPS6069898A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6069898A
公开(公告)日：1985-04-20
申请号：JP17758483
申请日：1983-09-26
申请人： TOSHIBA KK
发明人： TANAKA SUMIO , SAITOU SHINJI , ATSUMI SHIGERU
IPC分类号： G11C17/00 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/18 , G11C16/06 , H01L27/10
摘要： PURPOSE:To shorten the chip enable access time by providing a circuit which sets a reference potential as well as a bit line to the low level when a chip is not selected. CONSTITUTION:When the chip is changed from the selected state to the non- selected state, a chip enable signal CE' is changed from the low level to the high level, and a bit line 16 is discharged to the low level. Since an n-channel FET23 is connected to a connection point 27, the potential of the connection point 27 becomes low-level when the chip is changed to the non-selected state. When the chip is changed from the non-selected state to the selected state again, P-channel FETs 11 and 21 are turned on, and the bit line 16 is charged, but potentials of connection points 17 and 27 are raised in an approximately equal speed after chip selection because not only the bit line 16 and the connection point 17 but also the connection point 27 in the reference potential side are set to the low level when the chip is in the non-selected state. Therefore, sufficient detection by a differential amplifier 1 is possible.

18. 发明专利

JPS6069892A DECODING CIRCUIT OF NON-VOLTATILE MEMORY 失效
公开(公告)号：JPS6069892A
公开(公告)日：1985-04-20
申请号：JP17758583
申请日：1983-09-26
申请人： TOSHIBA KK
发明人： ATSUMI SHIGERU , SAITOU SHINJI , TANAKA SUMIO
IPC分类号： G11C11/413 , G11C11/34
摘要： PURPOSE:To extend the Vcc margin and perform operations in a high speed by using an intrinsic FET having a weak back gate bias effect as a transfer gate provided between a predecoder and an inverter. CONSTITUTION:A circuit is constituted with a P-channel active load FETT11 whose gate a voltage Vss is given to and at least two FETs T12-T13 connected in series, and enhancement FETs T1 and T2 are substituted with intrinsic N-channel FETs (I-type N-channel FETs) T6 and T7. Since a threshold voltage Vth of the intrinsic FET is about zero (Vth 0V) (that of the enhancement FET is about 0.8V) and the impurity concentration in the channel part is low, therefore the substrate bias effect is weak. Consequently, the potential in a node N2 is charged to the high level sufficiently quickly by FETs T6 and T7, and the Vcc margin is extended and operations are performed in a high speed.

19. 发明专利

JPS5987697A NONVORATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS5987697A
公开(公告)日：1984-05-21
申请号：JP19711082
申请日：1982-11-10
申请人： TOSHIBA KK
发明人： TANAKA SUMIO , ATSUMI SHIGERU
IPC分类号： G11C16/06 , G11C17/00 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent current that flows in a memory cell from becoming above a specified value at the time of data writing even when effective channel length of each memory cell becomes short by inserting a part between drain and source of an MOS transistor between a common source connecting point of plural memory cells and a reference potential point. CONSTITUTION:Current that flows in an MOS transistor 31 does not become above IO. This is because current that flows in the MOS transistor becomes saturation at a value when gate bias voltage is constant. Accordingly, if this saturated current value IO is prescribed as a maximum current value that can be flown in a memory cell 24 by design of channel width, channel length etc. of the MOS transistor 31, current above this value does not flow in the memory cell 24 in which data are being written. When the value of current that flows in the memory 24 is going to exceed IO, voltage of a circuit point 25 rises, and increase of current is obstructed.

20. 发明专利

JP2875068B2 失效
公开(公告)号：JP2875068B2
公开(公告)日：1999-03-24
申请号：JP18880791
申请日：1991-07-29
申请人： TOSHIBA KK
发明人： OOTSUKA NOBUAKI , TANAKA SUMIO
IPC分类号： G11C17/00 , G11C16/00 , G11C16/06 , H01L29/78 , H03K19/00

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