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11. 发明申请

US20090165020A1 COMMAND QUEUING FOR NEXT OPERATIONS OF MEMORY DEVICES 有权
标题翻译：用于下一次存储器件操作的命令队列
公开(公告)号：US20090165020A1
公开(公告)日：2009-06-25
申请号：US11962918
申请日：2007-12-21
申请人： Walter Allen , Sunil Atri , Joseph Khatami
发明人： Walter Allen , Sunil Atri , Joseph Khatami
IPC分类号： G06F3/00
CPC分类号： G06F13/4243
摘要： Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component.
摘要翻译：提出了有助于在处理器组件和存储器组件之间传送数据的系统和/或方法。转移控制器组件有助于部分地通过从相应的存储器组件接收数据的相应子集并且部分地基于期望的预定数据顺序排列相应的数据子集来部分地控制数据传输。处理器组件生成包括有助于按预定顺序排列数据的信息的传输图。处理器组件产生相应的命令子集，其提供给在各个存储器组件中对组件进行排队以从各个存储器组件检索所需的数据。每个存储器组件以独立和并行的方式对其队列组件中的命令进行服务，并将从存储器检索的数据传送到传输控制器组件，传输控制器组件可以按照预定义的顺序排列接收的数据以传送到处理器组件。

12. 发明申请

US20090164750A1 DATA COMMIT ON MULTICYCLE PASS COMPLETE WITHOUT ERROR 有权
标题翻译：数据通过多个通讯完成没有错误
公开(公告)号：US20090164750A1
公开(公告)日：2009-06-25
申请号：US11963200
申请日：2007-12-21
申请人： Sunil Atri , Robert Brent France , Walter Allen
发明人： Sunil Atri , Robert Brent France , Walter Allen
IPC分类号： G06F12/00
CPC分类号： G06F11/141 , G06F11/1441
摘要： A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.
摘要翻译：提供了一种能够防止在与存储器相关联的多周期完成数据提交期间的错误的系统和方法。该系统在存储器中采用事务缓冲器组件，其接收并临时存储与事务相关联的信息。基于存储在事务缓冲器组件中的信息，一旦整个事务完成，控制器组件就将数据子集编程到相应的存储单元。因此，如果在将用户数据传送到缓冲器期间交易中断，则存储在存储器中的数据不受影响，并且在恢复供电时仍然可以包含原始数据。如果事务缓冲器组件和存储器阵列之间的数据传输中断，则控制器组件可以在重新获取电源时从中断点完成传输，并且可以避免数据的部分存储。

13. 发明申请

US20060224817A1 NOR flash file allocation 审中-公开
标题翻译： NOR闪存文件分配
公开(公告)号：US20060224817A1
公开(公告)日：2006-10-05
申请号：US11096492
申请日：2005-03-31
申请人： Sunil Atri
发明人： Sunil Atri
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： An emulated file allocation table for a NOR flash memory may provide features that improve the performance or efficiency of the file allocation process. For example, the emulated file allocation table may include a slot or field which provides the information needed to convert from logical numbers to physical addresses. In some embodiments, this may reduce the demands on the system random access memory. In addition, the table may provide an entry which accommodates for deletion or replacement of sectors. In particular, it may provide a pointer for where to go in such circumstances. The provision of such a slot or field may reduce or eliminate the need to rewrite the file allocation table each time a cluster is replaced or deleted.
摘要翻译：用于NOR闪存的仿真文件分配表可以提供提高文件分配过程的性能或效率的特征。例如，仿真文件分配表可以包括提供从逻辑号转换到物理地址所需的信息的时隙或字段。在一些实施例中，这可以减少对系统随机存取存储器的需求。此外，该表还可以提供一个适用于删除或更换扇区的条目。特别地，它可以提供一个指针，用于在这种情况下去哪里。每次更换或删除集群时，提供这样的插槽或字段可以减少或消除重写文件分配表的需要。

14. 发明申请

US20060059385A1 Volatile storage based power loss recovery mechanism 有权
标题翻译：基于易失性存储的功率损耗恢复机制
公开(公告)号：US20060059385A1
公开(公告)日：2006-03-16
申请号：US10933862
申请日：2004-09-02
申请人： Sunil Atri , Sean Eilert
发明人： Sunil Atri , Sean Eilert
IPC分类号： G06F11/00
CPC分类号： G06F11/1441 , G11C5/141 , G11C14/00 , G11C16/102
摘要： According to some embodiments, power loss recovery information related to an active operation is stored in volatile memory. Upon detection of a power loss condition, the power loss recovery information is copied to non-volatile memory. Upon a return of power, the power loss recovery information is used to complete or correct the interrupted operation.
摘要翻译：根据一些实施例，与有效操作有关的功率损耗恢复信息被存储在易失性存储器中。在检测到功率损耗状况时，将功率损耗恢复信息复制到非易失性存储器。在电源恢复时，功率损耗恢复信息用于完成或纠正中断的操作。

15. 发明授权

US07953919B2 Physical block addressing of electronic memory devices 有权
标题翻译：电子存储器件的物理块寻址
公开(公告)号：US07953919B2
公开(公告)日：2011-05-31
申请号：US11963306
申请日：2007-12-21
申请人： Walter Allen , Sunil Atri , Joseph Khatami
发明人： Walter Allen , Sunil Atri , Joseph Khatami
IPC分类号： G06F12/06 , G06F13/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.
摘要翻译：介绍了有助于从存储器访问数据的系统和/或方法。电子存储器组件可以通过消除/减少使用逻辑块寻址并采用物理块寻址来减少数据访问时间。因此，数据访问与所存储的比特的物理位置直接相关联，并且减少或消除了在逻辑地址和物理地址之间进行转换的需要。这在非对称数据访问模式下可以更有效率。此外，可以包括对逻辑块寻址的传统支持以提供向后兼容性，混合模式操作或补充模式操作。

16. 发明授权

US07675776B2 Bit map control of erase block defect list in a memory 有权
标题翻译：存储器中擦除块缺陷列表的位图控制
公开(公告)号：US07675776B2
公开(公告)日：2010-03-09
申请号：US11963286
申请日：2007-12-21
申请人： Walter Allen , Robert France , Sunil Atri
发明人： Walter Allen , Robert France , Sunil Atri
IPC分类号： G11C16/06
CPC分类号： G11C29/76
摘要： Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.
摘要翻译：介绍了在包括非易失性存储器的存储器件中促进坏块管理的系统和方法。存储器设备的一个或多个存储器块都与一个或多个附加的专用位相关联，这些专用位便于指示相关联的存储器块是否有缺陷。称为坏块位的这些附加位可以存储在存储器件内的基于硬件的存储机制中。一旦在存储器块中检测到缺陷，则可以将相关联的坏块位中的至少一个设置为指示存储器块有缺陷。如果与存储块相关联的至少一个坏块比特指示存储块是有缺陷的，则可以防止对存储块的访问。

17. 发明申请

US20090300318A1 ADDRESS CACHING STORED TRANSLATION 有权
标题翻译：地址缓存存储翻译
公开(公告)号：US20090300318A1
公开(公告)日：2009-12-03
申请号：US12127919
申请日：2008-05-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0246
摘要： Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.
摘要翻译：呈现促进逻辑块地址（LBA）到与存储器组件相关联的物理块地址（PBA）转换的系统和/或方法。所公开的主题采用优化的块地址（BA）组件，其可以有助于部分地基于预定的优化标准来促进将LBA缓存到存储器控制器组件内的PBA转换，以便于改进与存储器组件相关联的数据的访问。预定的优化标准可以涉及从LBA被访问以来的时间长度，LBA已经访问的次数，与LBA相关的数据的数据大小和/或其他因素。可以使用LBA到PBA转换来促进使用高速缓存的转换来访问LBA和/或相关联的数据，而不是执行各种功能来确定翻译。

18. 发明申请

US20090172345A1 TRANSLATION MANAGEMENT OF LOGICAL BLOCK ADDRESSES AND PHYSICAL BLOCK ADDRESSES 有权
标题翻译：逻辑块地址和物理地址的翻译管理
公开(公告)号：US20090172345A1
公开(公告)日：2009-07-02
申请号：US11966919
申请日：2007-12-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/7201
摘要： Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.
摘要翻译：呈现促进与存储器组件相关联的PBA和LBA转换的系统和/或方法。存储器控制器组件有助于确定哪个存储器组件，擦除块，页面和数据块包含存储期望的LBA和/或相关联的数据的PBA。存储器控制器组件便于控制计算功能，表查找功能和/或搜索功能的性能，以定位所需的LBA。内存控制器组件部分地基于预定义的优化标准生成配置顺序，以促进翻译的优化性能。存储器控制器组件和/或相关联的存储器组件可以被配置为使得使用期望的转换功能以期望的顺序确定翻译属性，以部分地基于预定义的优化标准来确定相应的翻译属性。 LBA到PBA转换可以由存储器组件并行执行。

19. 发明申请

US20060004950A1 Flash memory file system having reduced headers 审中-公开
标题翻译：闪存文件系统具有缩减的标题
公开(公告)号：US20060004950A1
公开(公告)日：2006-01-05
申请号：US10880993
申请日：2004-06-30
申请人： Jeffrey Wang , John Rudelic , Sujaya Srinivasan , Sunil Atri
发明人： Jeffrey Wang , John Rudelic , Sujaya Srinivasan , Sunil Atri
IPC分类号： G06F12/00
CPC分类号： G06F11/1435
摘要： A flash memory file system includes fragments and headers. The headers have a reduced number of states.
摘要翻译：闪存文件系统包括片段和标题。标题具有减少的状态数。

20. 发明申请

US20050071731A1 Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices 有权
标题翻译：用于支持ECC启用的存储器件中的功率损耗恢复的方法，系统和装置
公开(公告)号：US20050071731A1
公开(公告)日：2005-03-31
申请号：US10672998
申请日：2003-09-25
申请人： Sunil Atri , John Rudelic
发明人： Sunil Atri , John Rudelic
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1068
摘要： A technique for coalesced PLR status bits in an ECC enabled flash memory.
摘要翻译：一种用于ECC启用闪存中的合并PLR状态位的技术。

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