专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050001260A1 EEPROM device and method of fabricating the same 失效
标题翻译： EEPROM装置及其制造方法
公开(公告)号：US20050001260A1
公开(公告)日：2005-01-06
申请号：US10872858
申请日：2004-06-21
申请人： Weon-Ho Park , Hyun-Khe Yoo
发明人： Weon-Ho Park , Hyun-Khe Yoo
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.
摘要翻译：存储器件包括第一导电类型的半导体衬底，存储晶体管，选择晶体管，浮动结区域，公共源极区域和位线结区域。存储晶体管位于半导体衬底上并且包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的存储晶体管栅极。栅极绝缘膜包括隧道绝缘膜。选择晶体管位于半导体衬底上并与存储晶体管栅极分离。选择晶体管包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的选择晶体管栅极。在隧道绝缘膜下方的半导体衬底上，由第二导电类型形成浮接区。第二导电类型的公共源极区域形成在与存储晶体管栅极相邻并且与浮置结区域分离的半导体衬底上。第二导电类型的位线结区域形成在与选择晶体管栅极相邻的半导体衬底上，并与浮置结区域分离，其中公共源极区域包括具有第一掺杂浓度的单结区域和深度公共源极区域比浮置结区域和位线结区域的深度浅。

12. 发明授权

US08432742B2 Non-volatile memory device, system, and cell array 有权
标题翻译：非易失性存储器件，系统和单元阵列
公开(公告)号：US08432742B2
公开(公告)日：2013-04-30
申请号：US13114120
申请日：2011-05-24
申请人： Chang-Min Jeong , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
发明人： Chang-Min Jeong , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C16/0483
摘要： A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.
摘要翻译：一种非易失性存储单元阵列，包括由施加到扇区选择线的电压控制的扇区选择晶体管，与扇区选择晶体管串联连接的第一至第四存储器单元，连接在第一存储单元与第二存储单元之间的第一公共源极线以及连接在第三存储单元和第四存储单元之间并与第一公共源极线分离的第二公共源极线。向第一公共源极线施加第一电压，并且将不同于第一电压的第二电压施加到第二公共源极线。

13. 发明申请

US20120181607A1 SEMICONDUCTOR DEVICES HAVING ASYMMETRIC DOPED REGIONS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有不对称区域的半导体器件及其制造方法
公开(公告)号：US20120181607A1
公开(公告)日：2012-07-19
申请号：US13352194
申请日：2012-01-17
申请人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
发明人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
IPC分类号： H01L27/088
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/0207 , H01L27/11504 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L29/7883
摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.
摘要翻译：半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。第二水平宽度大于第一水平宽度，第二深度比第一深度浅。彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。还描述了相关的制造方法。

14. 发明申请

US20080089136A1 NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF OPERATING THE SAME 失效
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US20080089136A1
公开(公告)日：2008-04-17
申请号：US11870762
申请日：2007-10-11
申请人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
发明人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
IPC分类号： G11C11/34 , H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.
摘要翻译：非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。第一感测线和第一字线在基板上彼此平行地相邻地形成。第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。耗尽沟道区形成在第一感测线下方的衬底的上部。在由第一感测线和第一字线露出的衬底的上部形成杂质区。

15. 发明申请

US20080008003A1 Non-Volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20080008003A1
公开(公告)日：2008-01-10
申请号：US11789003
申请日：2007-04-23
申请人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.
摘要翻译：非易失性存储器件包括存储器单元块，第一切换块和第二切换块。多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管它连接到源线。第一切换块选择性地将全局位线连接到本地位线，并且第二切换块以预定位数为单位来控制存储单元块中的存储单元。第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

16. 发明申请

US20060199334A1 EEPROM device and method of fabricating the same 失效
标题翻译： EEPROM装置及其制造方法
公开(公告)号：US20060199334A1
公开(公告)日：2006-09-07
申请号：US11418425
申请日：2006-05-04
申请人： Weon-Ho Park , Hyun-Khe Yoo
发明人： Weon-Ho Park , Hyun-Khe Yoo
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.
摘要翻译：存储器件包括第一导电类型的半导体衬底，存储晶体管，选择晶体管，浮动结区域，公共源极区域和位线结区域。存储晶体管位于半导体衬底上并且包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的存储晶体管栅极。栅极绝缘膜包括隧道绝缘膜。选择晶体管位于半导体衬底上并与存储晶体管栅极分离。选择晶体管包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的选择晶体管栅极。在隧道绝缘膜下方的半导体衬底上，由第二导电类型形成浮接区。第二导电类型的公共源极区域形成在与存储晶体管栅极相邻并且与浮置结区域分离的半导体衬底上。第二导电类型的位线结区域形成在与选择晶体管栅极相邻的半导体衬底上，并与浮置结区域分离，其中公共源极区域包括具有第一掺杂浓度的单结区域和深度公共源极区域比浮置结区域和位线结区域的深度浅。

17. 发明授权

US08698239B2 Semiconductor devices having asymmetric doped regions and methods of fabricating the same 有权
标题翻译：具有不对称掺杂区域的半导体器件及其制造方法
公开(公告)号：US08698239B2
公开(公告)日：2014-04-15
申请号：US13352194
申请日：2012-01-17
申请人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
发明人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
IPC分类号： H01L29/66 , H01L29/423 , H01L29/788 , H01L21/28 , H01L27/115 , H01L27/02
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/0207 , H01L27/11504 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L29/7883
摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.
摘要翻译：半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。第二水平宽度大于第一水平宽度，第二深度比第一深度浅。彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。还描述了相关的制造方法。

18. 发明申请

US20120044772A1 NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY 有权
标题翻译：非易失性存储器件，系统和细胞阵列
公开(公告)号：US20120044772A1
公开(公告)日：2012-02-23
申请号：US13114120
申请日：2011-05-24
申请人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
发明人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
IPC分类号： G11C16/10 , G11C16/06 , G11C16/04
CPC分类号： G11C16/06 , G11C16/0483
摘要： A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.
摘要翻译：一种非易失性存储单元阵列，包括由施加到扇区选择线的电压控制的扇区选择晶体管，与扇区选择晶体管串联连接的第一至第四存储器单元，连接在第一存储单元与第二存储单元之间的第一公共源极线以及连接在第三存储单元和第四存储单元之间并与第一公共源极线分离的第二公共源极线。向第一公共源极线施加第一电压，并且将不同于第一电压的第二电压施加到第二公共源极线。

19. 发明授权

US07253058B2 Method of manufacturing NOR-type mask ROM device and semiconductor device including the same 失效
公开(公告)号：US07253058B2
公开(公告)日：2007-08-07
申请号：US10899136
申请日：2004-07-27
申请人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
发明人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
IPC分类号： H01L21/8234
CPC分类号： H01L27/11266 , H01L21/823462 , H01L27/105 , H01L27/112 , H01L27/11293
摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

20. 发明授权

US06916711B2 EEPROM memory cell and method of forming the same 失效
标题翻译： EEPROM存储单元及其形成方法
公开(公告)号：US06916711B2
公开(公告)日：2005-07-12
申请号：US10819515
申请日：2004-04-07
申请人： Hyun-Khe Yoo
发明人： Hyun-Khe Yoo
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42324
摘要： An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a gate electrode layer constituting a sensing line. This leads to increases in opposite areas of a floating gate and a control gate of a sensing transistor, and a decrease in an area of the floating gate in the substrate. The method of forming an EEPROM memory cell comprises forming a trench in an active area in which a sensing transistor of the substrate will be formed; forming a gate insulation layer including a tunneling insulation layer on an entire surface of the substrate including an inside of the trench; conformally forming a first conductive layer covering the inside of the trench after forming the gate insulation layer; conformally forming a dielectric layer on the first conductive layer; forming a floating gate by patterning the first conductive layer; and stacking and patterning a second conductive layer on the dielectric layer to form a word line and a sensing line.
摘要翻译：提供了EEPROM存储单元及其形成方法。浮动栅极的一部分形成在形成在衬底上的沟槽的壁上。沟槽的内部填充有构成感测线的栅极电极层。这导致感测晶体管的浮置栅极和控制栅极的相对区域的增加以及衬底中浮置栅极的面积的减小。形成EEPROM存储单元的方法包括：在有源区中形成沟槽，在有源区中将形成衬底的感测晶体管; 在包括所述沟槽的内部的所述衬底的整个表面上形成包括隧道绝缘层的栅极绝缘层; 在形成栅极绝缘层之后，保形地形成覆盖沟槽内部的第一导电层; 在第一导电层上共形成介电层; 通过图案化第一导电层形成浮栅; 并且在介电层上堆叠和图案化第二导电层以形成字线和感测线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式