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11. 发明申请

US20110300704A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20110300704A1
公开(公告)日：2011-12-08
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/283
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

12. 发明申请

US20100159689A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20100159689A1
公开(公告)日：2010-06-24
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/768
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

13. 发明授权

US07364990B2 Epitaxial crystal growth process in the manufacturing of a semiconductor device 有权
标题翻译：外延晶体生长工艺制造半导体器件
公开(公告)号：US07364990B2
公开(公告)日：2008-04-29
申请号：US11301029
申请日：2005-12-13
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： C30B21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
摘要翻译：第一和第二初步外延层从绝缘层的开口中的单晶种子生长直到第一和第二外延层彼此连接。当正在生长第一和第二初步外延层时，在位于第一和第二初步外延层之间的绝缘层的一部分上形成具有非晶状态的材料的连接结构。然后将具有非晶态的材料变成具有单晶态的材料。因此，第一外延层和第二外延层的部分通过连接结构彼此连接，使得外延层和连接结构构成无空隙的单晶结构层，用作沟道层等半导体器件。

14. 发明申请

US20060292880A1 Methods of fabricating p-type transistors including germanium channel regions and related devices 有权
标题翻译：制造包括锗通道区域和相关器件的p型晶体管的方法
公开(公告)号：US20060292880A1
公开(公告)日：2006-12-28
申请号：US11447436
申请日：2006-06-06
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H02N6/00 , H01L21/302
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/02675 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L29/16
摘要： A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated, for example, by applying a laser to a portion of the non-crystalline germanium layer. Related devices are also discussed.
摘要翻译：制造晶体管器件的方法包括在种子层上形成非结晶锗层。选择性地将非结晶锗层局部加热至其熔点，以在籽晶层上形成单晶锗层。可以例如通过对非晶锗层的一部分施加激光来选择性地局部加热非晶锗层。还讨论了相关设备。

15. 发明授权

US07998851B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US07998851B2
公开(公告)日：2011-08-16
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

16. 发明申请

US20070132022A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070132022A1
公开(公告)日：2007-06-14
申请号：US11301029
申请日：2005-12-13
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L27/12
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
摘要翻译：第一和第二初步外延层从绝缘层的开口中的单晶种子生长直到第一和第二外延层彼此连接。当正在生长第一和第二初步外延层时，在位于第一和第二初步外延层之间的绝缘层的一部分上形成具有非晶状态的材料的连接结构。然后将具有非晶状态的材料变成具有单晶态的材料。因此，第一外延层和第二外延层的部分通过连接结构彼此连接，使得外延层和连接结构构成无空隙的单晶结构层，用作沟道层等半导体器件。

17. 发明申请

US20060211262A1 Methods of laterally forming single crystalline thin film regions from seed layers 有权
标题翻译：从种子层横向形成单晶薄膜区域的方法
公开(公告)号：US20060211262A1
公开(公告)日：2006-09-21
申请号：US11378731
申请日：2006-03-17
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02645 , H01L21/02675 , H01L27/0688 , H01L27/1285 , H01L29/78675
摘要： A method of forming an integrated circuit can be provided by successively laterally forming single crystalline thin film regions from an amorphous thin film using a lower single crystalline seed layer.
摘要翻译：可以通过使用较低的单晶种子层从非晶薄膜连续横向地形成单晶薄膜区域来提供形成集成电路的方法。

18. 发明授权

US07553742B2 Method(s) of forming a thin layer 有权
标题翻译：形成薄层的方法
公开(公告)号：US07553742B2
公开(公告)日：2009-06-30
申请号：US11329158
申请日：2006-01-11
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/76
CPC分类号： C30B25/04 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.
摘要翻译：一种形成薄层的方法，包括提供通过绝缘图案中的开口局部暴露的第一单晶硅层，并在第一单晶硅层上形成外延层，并在绝缘图案上形成非晶硅层，非晶硅层，其具有与外延层相邻的第一部分和与第一部分间隔开的第二部分，其中非晶硅层在第一部分和第二部分以基本上相同的速率形成在绝缘图案上。可以将非晶硅层形成为均匀的厚度而没有变薄的缺陷。

19. 发明授权

US07537980B2 Method of manufacturing a stacked semiconductor device 有权
标题翻译：叠层半导体器件的制造方法
公开(公告)号：US07537980B2
公开(公告)日：2009-05-26
申请号：US11510622
申请日：2006-08-28
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/336 , H01L29/94 , C30B33/06
CPC分类号： H01L21/76879 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02675 , H01L21/28525 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/535 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the first opening. A second SEG process may be performed to form a second plug filling the first opening. A third SEG process may be carried out to form a first channel layer on the first insulation interlayer pattern. A second insulation interlayer may be formed on the first channel layer. The second insulation interlayer, the first channel layer and the second plug arranged on the first plug may be removed to expose the first plug. The first plug may be removed to form a serial opening. The serial opening may be filled with a metal wiring.
摘要翻译：在制造叠层半导体器件的方法中，可以制备包括杂质区的晶种层。可以在种子层上形成具有第一开口的第一绝缘层间图案。可以执行第一SEG过程以形成部分填充第一开口的第一插塞。可以执行第二SEG过程以形成填充第一开口的第二塞子。可以执行第三SEG处理以在第一绝缘夹层图案上形成第一沟道层。可以在第一沟道层上形成第二绝缘中间层。布置在第一插头上的第二绝缘中间层，第一沟道层和第二插塞可以被去除以暴露第一插塞。可以移除第一个插头以形成串行开口。串行开口可以用金属布线填充。

20. 发明授权

US07459353B2 Methods of laterally forming single crystalline thin film regions from seed layers 有权
标题翻译：从种子层横向形成单晶薄膜区域的方法
公开(公告)号：US07459353B2
公开(公告)日：2008-12-02
申请号：US11378731
申请日：2006-03-17
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02645 , H01L21/02675 , H01L27/0688 , H01L27/1285 , H01L29/78675
摘要： A method of forming an integrated circuit can be provided by successively laterally forming single crystalline thin film regions from an amorphous thin film using a lower single crystalline seed layer.
摘要翻译：可以通过使用较低的单晶种子层从非晶薄膜连续横向地形成单晶薄膜区域来提供形成集成电路的方法。

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