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11. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

12. 发明申请

US20110065244A1 ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE 有权
标题翻译：具有改进的抗电弧和电容的非对称FINFET器件
公开(公告)号：US20110065244A1
公开(公告)日：2011-03-17
申请号：US12559996
申请日：2009-09-15
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/66795
摘要： A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region.
摘要翻译：一种用于形成鳍状场效应晶体管（finFET）器件的方法包括：在衬底中形成翅片结构，形成垂直于翅片结构的栅极堆叠结构，并以一定角度（...）将离子注入到衬底中以形成源极区域和漏极区域，其中角度（θ）相对于源极区域是倾斜的。

13. 发明授权

US08981478B2 Recessed source and drain regions for FinFETs 有权
标题翻译：嵌入式FinFET的源极和漏极区域
公开(公告)号：US08981478B2
公开(公告)日：2015-03-17
申请号：US13611335
申请日：2012-09-12
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
摘要翻译：半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。

14. 发明授权

US08816327B2 Nanowire efuses 有权
标题翻译：纳米线efuses
公开(公告)号：US08816327B2
公开(公告)日：2014-08-26
申请号：US13611081
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/78 , H01L23/525
CPC分类号： H01L29/785 , H01H2085/0283 , H01H2300/036 , H01L23/5256 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.
摘要翻译：示出了电可编程熔丝及其形成方法，其包括在基板上的第一焊盘和第二焊盘之间形成导线，在焊丝的一部分周围形成阻挡结构，以及在焊丝上沉积金属层，第二垫以形成金属化合物，其中所述金属化合物完全穿透所述阻挡结构内的所述金属丝的所述部分。

15. 发明授权

US08669615B1 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权
标题翻译：金属门功能工程技术可实现多个阈值电压FINFET器件
公开(公告)号：US08669615B1
公开(公告)日：2014-03-11
申请号：US13611257
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。在一个方面，提供一种FIN FET器件。 FIN FET器件包括在BOX上具有氧化物层和SOI层的SOI晶片和在氧化物层和SOI层中图案化的多个鳍状物; 翅片上的界面氧化物; 和界面氧化物上的至少一个栅极堆叠，所述栅极堆叠具有（i）存在共形栅极电介质层，（ii）共形栅极金属层，和（iii）共形功函数设定材料层。存在于栅极堆叠中的共形栅极金属层的体积和共形功函数设定材料层的体积与散热片的间距成正比。

16. 发明申请

US20130153997A1 HYBRID CMOS NANOWIRE MESH DEVICE AND BULK CMOS DEVICE 有权
公开(公告)号：US20130153997A1
公开(公告)日：2013-06-20
申请号：US13328106
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/66545 , B82Y10/00 , B82Y40/00 , H01L27/088 , H01L27/1207 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和体CMOS器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和体CMOS器件的半导体结构。

17. 发明申请

US20130153993A1 HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH器件和FINFET器件
公开(公告)号：US20130153993A1
公开(公告)日：2013-06-20
申请号：US13328015
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/28 , B82Y99/00 , B82Y40/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和FINFET器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和FINFET器件的半导体结构。

18. 发明申请

US20130106496A1 NANOWIRE EFUSES 有权
公开(公告)号：US20130106496A1
公开(公告)日：2013-05-02
申请号：US13611081
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01H37/76
CPC分类号： H01L29/785 , H01H2085/0283 , H01H2300/036 , H01L23/5256 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.

19. 发明授权

US08404539B2 Self-aligned contacts in carbon devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US08404539B2
公开(公告)日：2013-03-26
申请号：US12832224
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/8238
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
摘要翻译：一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及在所述至少一个空腔中形成导电接触。

20. 发明授权

US08362568B2 Recessed contact for multi-gate FET optimizing series resistance 有权
标题翻译：嵌入式多栅极FET优化串联电阻
公开(公告)号：US08362568B2
公开(公告)日：2013-01-29
申请号：US12583933
申请日：2009-08-28
申请人： Chung-Hsun Lin , Josephine B. Chang
发明人： Chung-Hsun Lin , Josephine B. Chang
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L29/66636 , H01L29/785
摘要： A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h1) within the gate structure that is less than the height of the gate structure, and has a second height (h2) external to the gate structure, where h2 is less than h1. The transistor further includes a silicide layer disposed at least partially over the at least one channel external to the gate structure. Reducing the fin height external to the gate structure is shown to beneficially reduce parasitic resistance.
摘要翻译：可以称为多栅极晶体管或FinFET的晶体管包括具有长度，宽度和高度的栅极结构。晶体管还包括通过栅极结构的宽度的源极区域和漏极区域之间的至少一个导电沟道或鳍。通道在门结构内具有小于栅极结构的高度的第一高度（h1），并且具有栅极结构外部的第二高度（h2），其中h2小于h1。晶体管还包括至少部分地设置在栅极结构外部的至少一个沟道上的硅化物层。降低栅极结构外部的翅片高度被显示有利地减少寄生电阻。

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