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11. 发明授权

US07380131B1 Copy protection without non-volatile memory 有权
标题翻译：复制保护，不带非易失性存储器
公开(公告)号：US07380131B1
公开(公告)日：2008-05-27
申请号：US09765907
申请日：2001-01-19
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L9/00
CPC分类号： H04L9/0866
摘要： An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.
摘要翻译： FPGA包括多个可配置逻辑元件，配置电路，解密电路和指纹元件。指纹元件产生指示，其指示FPGA独有的固有制造工艺变化。该指纹被用作加密系统的关键，防止非法使用和/或复制配置数据。在一些实施例中，形成在FPGA上的各种电路元件的传播延迟用于生成指纹。在一个实施例中，使用振荡器的特定频率来产生指纹。在一些实施例中，可以使用可测量值的比率来生成指纹。在其他实施例中，晶体管阈值电压的差异被用于生成指纹。在其他实施例中，使用线宽的变化来生成指纹。

12. 发明授权

US07254800B1 Methods of providing error correction in configuration bitstreams for programmable logic devices 有权
标题翻译：在可编程逻辑器件的配置比特流中提供纠错的方法
公开(公告)号：US07254800B1
公开(公告)日：2007-08-07
申请号：US10787683
申请日：2004-02-26
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.
摘要翻译：在可编程逻辑器件（PLD）的配置比特流中提供纠错的方法。虽然可以使用任何纠错方法，但是在一个实施例中，将汉明码应用于配置比特流中的指令，同时将产品代码应用于配置数据。因此，汉明码所需的较高开销仅适用于比特流中的几个字。在接收到包含汉明码的单词时纠正指令，因此即使发生传输错误，指令也能正确执行。然而，配置数据可以存储在配置存储器中而不进行校正。使用产品代码，当接收到奇偶校验字时，直到发送结束，才知道错误位的确切位置。此时，在启用新加载的设计之前，PLD可以返回并纠正配置数据中的错误位。

13. 发明授权

US07200235B1 Error-checking and correcting decryption-key memory for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的错误检查和纠正解密密钥存储器
公开(公告)号：US07200235B1
公开(公告)日：2007-04-03
申请号：US10147589
申请日：2002-05-17
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L9/14 , H04L1/00
CPC分类号： G06F12/1425 , G06F21/57 , G06F21/79 , G06Q20/3829 , H04L9/0637 , H04L9/0897 , H04L2209/34
摘要： Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. The PLD additionally includes error-correction circuitry that receives each key and associated ECC and performs an error correction before conveying the resulting error-corrected key to a decryptor.
摘要翻译：描述了检测和纠正解密密钥错误的电路。在一个示例中，可编程逻辑设备包括具有多个解密密钥字段的解密密钥存储器，并且对于每个密钥字段，包括相关联的纠错码（ECC）字段。 PLD还包括纠错电路，其接收每个密钥和相关联的ECC，并在将所得到的纠错密钥传送给解密器之前执行纠错。

14. 发明授权

US07187597B1 Integrated circuit with circuitry for overriding a defective configuration memory cell 有权
标题翻译：具有用于覆盖缺陷配置存储单元的电路的集成电路
公开(公告)号：US07187597B1
公开(公告)日：2007-03-06
申请号：US11218415
申请日：2005-09-01
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/10 , G11C5/063 , G11C29/24 , G11C29/816 , G11C29/846
摘要： An integrated circuit and a method for configuring programmable logic thereof are described. A data register and an address register are coupled to an array of memory cells of the integrated circuit. Address storage is configurable for storing an address associated configuration data targeted for being written to at least one defective memory cell of the array of memory cells. Data storage is configured to store the configuration data associated with the at least one defective memory cell. A controller is configured to cause the address to be loaded into the address register and the configuration data to be loaded into the data register. The controller is configured to maintain a write state for continually writing the configuration data to the array of memory cells responsive to the address during operation of the integrated circuit.
摘要翻译：描述了用于配置其可编程逻辑的集成电路和方法。数据寄存器和地址寄存器耦合到集成电路的存储单元阵列。地址存储器可配置为存储针对要写入到存储器单元阵列的至少一个有缺陷的存储器单元的地址相关联的配置数据。数据存储被配置为存储与至少一个有缺陷的存储器单元相关联的配置数据。控制器被配置为使得地址被加载到地址寄存器中，并且配置数据被加载到数据寄存器中。控制器被配置为保持写入状态，以响应于在集成电路的操作期间的地址，将配置数据连续地写入存储器单元阵列。

15. 发明授权

US07143295B1 Methods and circuits for dedicating a programmable logic device for use with specific designs 有权
标题翻译：专用可编程逻辑器件用于特定设计的方法和电路
公开(公告)号：US07143295B1
公开(公告)日：2006-11-28
申请号：US10199535
申请日：2002-07-18
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32
CPC分类号： H04L9/0637 , G01R31/318555 , G06F21/76 , H04L9/3247 , H04L2209/12 , H04L2209/38
摘要： Disclosed are methods and circuits that enable PLD vendors to dedicate PLDs for use with one or more specified designs. The PLD is programmed to store an indicator related to a specific design, for example, a hash function of the design, and to compare an indicator calculated within the PLD from an expression of the design (such as a bitstream) with the stored indicator. Only if the comparison matches is the PLD programmed to implement the design.
摘要翻译：公开了使PLD供应商能够将PLD用于一个或多个指定设计的方法和电路。 PLD被编程为存储与特定设计相关的指示符，例如设计的散列函数，并且将PLD中计算的指示符与设计（例如比特流）的表达式与存储的指示符进行比较。只有比较匹配是编程实现设计的PLD。

16. 发明授权

US07138827B1 Programmable logic device with time-multiplexed interconnect 有权
公开(公告)号：US07138827B1
公开(公告)日：2006-11-21
申请号：US10810034
申请日：2004-03-26
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/177
CPC分类号： G06F17/5054
摘要： A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

17. 发明授权

US07103685B1 Bitstream compression with don't care values 有权
标题翻译：比特流压缩与不关心的价值
公开(公告)号：US07103685B1
公开(公告)日：2006-09-05
申请号：US10759755
申请日：2004-01-16
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F13/00
CPC分类号： H03M7/3084 , G06F17/5054
摘要： A method and system for processing a plurality of multi-bit configuration words for configuring a programmable logic device. One or more of bits of the multi-bit configuration words are identified as “Don't Care” configuration bits that do not affect the functionality of the programmable logic device. These “Don't Care” configuration bits may or may not be related to the specific configuration of the programmable logic device. A lossy compression operation is performed on the multi-bit configuration words thereby creating a compressed data set. The identified “Don't Care” configuration bits are used during the compression operation. For example, the compression operation may include (1) maintaining a compression buffer of previously compressed configuration words, and (2) comparing configuration words to be compressed with the configuration words in the compression buffer, wherein the “Don't Care” configuration bits are deemed to result in matches during the comparison.
摘要翻译：一种用于处理用于配置可编程逻辑器件的多个多位配置字的方法和系统。多位配置字中的一个或多个位被标识为不影响可编程逻辑器件的功能的“不关心”配置位。这些“不关心”配置位可能或可能与可编程逻辑器件的具体配置无关。对多位配置字执行有损压缩操作，从而创建压缩数据集。在压缩操作期间使用标识的“不关心”配置位。例如，压缩操作可以包括（1）维持先前压缩的配置字的压缩缓冲器，以及（2）将要压缩的配置字与压缩缓冲器中的配置字进行比较，其中“不关心”配置位在比较期间被视为导致比赛。

18. 发明授权

US06996713B1 Method and apparatus for protecting proprietary decryption keys for programmable logic devices 有权
标题翻译：用于保护可编程逻辑器件的专用解密密钥的方法和装置
公开(公告)号：US06996713B1
公开(公告)日：2006-02-07
申请号：US10112838
申请日：2002-03-29
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F1/26
CPC分类号： G06F21/76
摘要： Described are methods and circuits of programming a programmable logic device with encrypted configuration data using one or more secure decryption keys. Configurable resources within PLDS in accordance with one embodiment are divided into first and second collections of configurable interconnect resources separated by a collection of switches. One collection of resources has access to one or more decryption keys required to decrypt the encrypted configuration data. The switches protect the proprietary keys by providing a secure boundary around the portion granted key access during the decryption process. Closing the switches after configuration clears user memory to prevent users from accessing stored versions of the proprietary keys.
摘要翻译：描述了使用一个或多个安全解密密钥对具有加密配置数据的可编程逻辑设备进行编程的方法和电路。根据一个实施例的PLDS内的可配置资源被划分为由开关集合分隔开的可配置互连资源的第一和第二集合。一组资源可以访问解密加密的配置数据所需的一个或多个解密密钥。交换机通过在解密过程中为授予密钥访问的部分提供安全边界来保护专有密钥。配置后关闭交换机会清除用户内存，以防止用户访问专有密钥的存储版本。

19. 发明授权

US06981153B1 Programmable logic device with method of preventing readback 有权
标题翻译：可编程逻辑器件，具有防止回读的方法
公开(公告)号：US06981153B1
公开(公告)日：2005-12-27
申请号：US09724975
申请日：2000-11-28
申请人： Raymond C. Pang , Walter N. Sze , John M. Thendean , Stephen M. Trimberger , Jennifer Wong
发明人： Raymond C. Pang , Walter N. Sze , John M. Thendean , Stephen M. Trimberger , Jennifer Wong
IPC分类号： H03K19/173 , G06F17/50 , G06F21/00 , G09C1/00 , H04L9/10 , G06F12/14
CPC分类号： H04N21/23476 , G06F17/5054 , G06F21/76
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
摘要翻译：有时期望保护PLD中使用的设计不被复制。如果设计存储在与PLD不同的设备中并且通过比特流读入PLD，则在加载到用于配置PLD的配置存储器单元之前，设计可以在PLD中被读入PLD并被解密并被解密。根据本发明，在这种设备中，提供了一种方法，用于防止在被加载到PLD中时将设计从PLD解密的状态下读回PLD。

20. 发明授权

US06980026B1 Structures and methods for reducing power consumption in programmable logic devices 有权
标题翻译：用于降低可编程逻辑器件功耗的结构和方法
公开(公告)号：US06980026B1
公开(公告)日：2005-12-27
申请号：US10737603
申请日：2003-12-16
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17784
摘要： Structures and methods that can be used to reduce power consumption in programmable logic devices (PLDs). Varying delays on the input paths of a PLD lookup table (LUT) can cause the nodes within the LUT (including the LUT output signal) to change state several times each time the input signals change state. Therefore, a programmable logic block for a PLD is provided that registers the LUT input signals instead of, or in addition to, the LUT output signal. The delays on the input paths are equalized and “glitching” on the LUT nodes is greatly reduced or eliminated. Thus, power consumption is reduced. Methods are also provided of reducing power consumption in PLDs by replacing single-bit registers on LUT output signals with multi-bit registers on LUT input signals, or by including multi-bit input registers in addition to the single-bit output registers.
摘要翻译：可用于降低可编程逻辑器件（PLD）功耗的结构和方法。每当输入信号改变状态时，PLD查找表（LUT）的输入路径上的不同延迟可以使LUT内的节点（包括LUT输出信号）改变状态多次。因此，提供了用于PLD的可编程逻辑块，其注册LUT输入信号，而不是或输出到LUT输出信号。输入路径上的延迟均衡，LUT节点上的“毛刺”大大减少或消除。因此，功耗降低。还提供了通过用LUT输入信号上的多位寄存器替换LUT输出信号上的单位寄存器，或者除了单位输出寄存器之外还包括多位输入寄存器来减少PLD中的功耗的方法。

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