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11. 发明授权

US06300819B1 Circuit including forward body bias from supply voltage and ground nodes 失效
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

12. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

13. 发明授权

US06232827B1 Transistors providing desired threshold voltage and reduced short channel effects with forward body bias 失效
标题翻译：晶体管提供期望的阈值电压和减少的短通道效应与前向偏置
公开(公告)号：US06232827B1
公开(公告)日：2001-05-15
申请号：US09078388
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.
摘要翻译：在一个实施例中，半导体电路包括具有主体的第一组场效应晶体管和包括净通道掺杂水平DL1的参数。该电路还包括导体，用于向主体提供第一电压以使第一组晶体管偏置，第一组晶体管在正向偏置时具有正向偏置阈值电压（VtFBB），其中DL1至少为25 高于第一组晶体管中的净通道掺杂水平，其将导致零体偏置阈值电压等于VtFBB，其中除了净通道掺杂水平之外的参数不变。在另一实施例中，半导体电路包括第一电路，其包括具有主体的第一组场效应晶体管。电路还包括第一电压源，以向主体提供第一电压，使得场效应晶体管具有正向体偏置，第一电压处于导致电路经历软错误故障率降低的水平，与当电路没有正向偏置时。

14. 发明授权

US06218895B1 Multiple well transistor circuits having forward body bias 失效
标题翻译：具有前向偏置的多个阱晶体管电路
公开(公告)号：US06218895B1
公开(公告)日：2001-04-17
申请号：US09078424
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.
摘要翻译：在本发明的一个实施例中，半导体电路包括衬底和形成在衬底中的第一阱。在第一阱中形成第一组场效应晶体管，并且具有第一主体。该电路包括第一体电压，以使第一组场效应晶体管偏转第一体。电路包括第一隔离结构，以在第一阱中容纳第一体电压。在另一实施例中，电路还包括具有非正向主体偏置的第二组场效应晶体管，并且第一隔离结构防止第一体电压影响第二组场效应晶体管的主体的电压。在另一个实施例中，与第二阱相邻的第二隔离结构在保持第二组场效应晶体管的第二阱中包含第二体电压。

15. 发明授权

US06593799B2 Circuit including forward body bias from supply voltage and ground nodes 有权
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06593799B2
公开(公告)日：2003-07-15
申请号：US09957996
申请日：2001-09-21
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H03K301
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

16. 发明授权

US06366156B1 Forward body bias voltage generation systems 有权
标题翻译：前向偏置电压发生系统
公开(公告)号：US06366156B1
公开(公告)日：2002-04-02
申请号：US09451661
申请日：1999-11-30
申请人： Siva G. Narendra , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： In some embodiments, In some embodiments, the invention includes an electrical system having a functional unit block (FUB) including field effect transistors (FETs). A distributed forward body bias (FBB) voltage generation system provides at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant FBB. In some embodiments, the system includes a constant differential voltage generator and a distributed body bias generator to receive a set of differential signals from the constant differential voltage generator and provide at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant forward body bias. In some embodiments, the system includes multiple body bias generators coupled to corresponding FUBs receive a set of differential signals from a single constant differential voltage generator. In other embodiments, multiple constant differential voltage generators provide multiple sets of differential signals to multiple body bias generators coupled to corresponding FUBs. Without the invention, significant changes in the FBB of FETs in different FUBs can induce a new source of variation which can nullify the advantages of FBB and actually increase parameter variations between FETs of different FUBs.
摘要翻译：在一些实施例中，在一些实施例中，本发明包括具有包括场效应晶体管（FET）的功能单元块（FUB）的电气系统。分布式正向偏置（FBB）电压产生系统向FUB的至少一些FET提供至少一个体偏置信号，使得至少一些FET具有恒定的FBB。在一些实施例中，该系统包括恒定差分电压发生器和分布式主体偏置发生器，以从该恒定差分电压发生器接收一组差分信号，并且向FUB的至少一些FET提供至少一个体偏置信号，所述至少一些所述FET具有恒定的前向体偏置。在一些实施例中，系统包括耦合到对应的FUB的多个体偏置发生器，其从单个恒定差分电压发生器接收一组差分信号。在其他实施例中，多个恒定差分电压发生器向耦合到对应的FUB的多个体偏置发生器提供多组差分信号。没有本发明，不同FUB中的FET的FBB的显着变化可以引起新的变化源，这可以消除FBB的优点，并且实际上增加了不同FUB的FET之间的参数变化。

17. 发明授权

US06849909B1 Method and apparatus for weak inversion mode MOS decoupling capacitor 失效
标题翻译：弱反转模式MOS去耦电容器的方法和装置
公开(公告)号：US06849909B1
公开(公告)日：2005-02-01
申请号：US09677698
申请日：2000-09-28
申请人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
发明人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
IPC分类号： H01L27/08 , H01L31/119 , H01L29/088 , H01L29/90
CPC分类号： H01L27/0811 , Y10S257/901
摘要： A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.
摘要翻译：描述了用于提供弱反型模式金属氧化物半导体（MOS）去耦电容器的方法和装置。在一个实施例中，增强型p沟道MOS（PMOS）晶体管由其功能与常用功能不同的栅极材料构成。在一个示例性实施方案中，使用铂硅酸盐（PtSi）。在替代实施例中，可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。在任一实施例中，晶体管的平带幅度偏移用于构造晶体管的材料的变化。当这种晶体管与连接到正电源电压的栅极引线连接，而其他引线连接到负（接地）电源电压时，会产生改进的去耦电容。

18. 发明授权

US07051295B2 IC design process including automated removal of body contacts from MOSFET devices 有权
标题翻译： IC设计过程包括从MOSFET器件自动移除主体触点
公开(公告)号：US07051295B2
公开(公告)日：2006-05-23
申请号：US10746759
申请日：2003-12-23
申请人： Siva G. Narendra , Daniel S. Klowden , James W. Tschanz , Nitin Borkar , Vivek K. De
发明人： Siva G. Narendra , Daniel S. Klowden , James W. Tschanz , Nitin Borkar , Vivek K. De
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.
摘要翻译：一种用于修改集成电路的IC设计布局的装置和方法，包括：访问初始IC设计布局，初始布局包括具有公共衬底的多个MOSFET器件; 以及去除所述MOSFET器件的多个体接触以产生第一修改的IC设计布局。

19. 发明授权

US07324328B2 Integrated ultracapacitor as energy source 有权
标题翻译：集成超级电容器作为能源
公开(公告)号：US07324328B2
公开(公告)日：2008-01-29
申请号：US11274187
申请日：2005-11-16
申请人： Siva G. Narendra , Shekhar Y. Borkar
发明人： Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01G9/00
CPC分类号： H01G9/155 , H01L23/5223 , H01L2924/0002 , Y02E60/13 , H01L2924/00
摘要： An ultracapacitor formed on a semiconductor substrate includes a plurality conductive layers with intervening dielectric layers. These layers form a plurality of capacitors which may be connected in parallel to store a charge for powering an electronic circuit or for performing a variety of integrated circuit applications. A plurality of ultracapacitors of this type may be connected in series or may be designed in stacked configuration for attaining a specific charge distribution profile.
摘要翻译：形成在半导体衬底上的超级电容器包括具有中间介电层的多个导电层。这些层形成多个电容器，其可以并联连接以存储用于为电子电路供电或用于执行各种集成电路应用的电荷。这种类型的多个超级电容器可以串联连接或者可以被设计成堆叠配置以获得特定的电荷分布曲线。

20. 发明授权

US07541782B2 System and method for extracting energy from an ultracapacitor 有权
标题翻译：从超级电容器中提取能量的系统和方法
公开(公告)号：US07541782B2
公开(公告)日：2009-06-02
申请号：US10811806
申请日：2004-03-30
申请人： Siva G. Narendra , Shekhar Y. Borkar
发明人： Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H02J7/00 , H02J7/06 , H02J7/24
CPC分类号： H01G9/14 , H01C3/20 , H01L23/5222 , H01L2924/0002 , H02J7/0065 , Y02E60/13 , H01L2924/00
摘要： An extraction system detects a voltage stored in a capacitor and then extracts energy from the capacitor when the voltage falls below a predetermined value. The capacitor may be an ultracapacitor formed in silicon or another semiconductor material, and the predetermined value may equal or be based on a minimum operating voltage of a load driven by the ultracapacitor. Once the energy is extracted, the system converts the energy into a voltage sufficient to continue driving the load. Energy extraction may be performed by a variety of circuits including a linear regulator, a switched capacitor voltage converter, an adiabatic amplifier, and a DC-to-DC boost converter. The system may further include a monitoring circuit which detects dynamic changes in the converted ultracapacitor voltage over to maintain the operating voltage of the load.
摘要翻译：提取系统检测存储在电容器中的电压，然后当电压降到预定值以下时从电容器中提取能量。电容器可以是在硅或另一种半导体材料中形成的超级电容器，并且预定值可以等于或基于由超级电容器驱动的负载的最小工作电压。一旦提取能量，系统将能量转换成足以继续驱动负载的电压。可以通过包括线性调节器，开关电容器电压转换器，绝热放大器和DC-DC升压转换器的各种电路来执行能量提取。该系统还可以包括监测电路，其检测转换的超级电容器电压的动态变化以维持负载的工作电压。

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