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11. 发明申请

US20050275437A1 Reset circuit 有权
标题翻译：复位电路
公开(公告)号：US20050275437A1
公开(公告)日：2005-12-15
申请号：US10998060
申请日：2004-11-29
申请人： Hideaki Suzuki , Hirokazu Yamazaki
发明人： Hideaki Suzuki , Hirokazu Yamazaki
IPC分类号： H03K3/356 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , H03K3/356008
摘要： A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.
摘要翻译：复位电路包括电源检测电路，掉电检测电路和输出电路。当电源电压的第一电压高于第一阈值时，电源检测电路输出第一信号，并且在上电和掉电期间当第一电压低于第一阈值时输出第二信号。当在掉电期间输出第二信号之后，当根据电源电压的第二电压变得低于第二阈值时，掉电检测电路输出第三信号。输出电路在上电时输出第一个信号时，输出从低电平变为高电平的上电复位信号，并在断电时输出第三个信号输出时从低电平变为高电平的掉电复位信号。

12. 发明授权

US06229728B1 Ferroelectric memory and method of testing the same 有权
标题翻译：铁电存储器和测试方法相同
公开(公告)号：US06229728B1
公开(公告)日：2001-05-08
申请号：US09296544
申请日：1999-04-22
申请人： Chikai Ono , Hirokazu Yamazaki
发明人： Chikai Ono , Hirokazu Yamazaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.
摘要翻译：铁电存储器包括存储器单元，存储单元连接到的一对位线，以及控制电路，其将从一个存储单元读取的数据输出到对应于一对位线之一的参考单元，另一个位线对。

13. 发明授权

US6072724A Semiconductor integrated circuit for generating plurality of different reference levels 失效
标题翻译：用于产生多个不同参考电平的半导体集成电路
公开(公告)号：US6072724A
公开(公告)日：2000-06-06
申请号：US902275
申请日：1997-07-29
申请人： Hirokazu Yamazaki
发明人： Hirokazu Yamazaki
IPC分类号： G11C16/06 , G11C11/56 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5621 , G11C11/5635 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Disclosed is an art making it possible that, in a reference cell circuit for outputting a plurality of different reference level signals, even if the number of transistors serving as reference cells and each having a floating gate increases, the time required for setting channel currents of the transistors will not increase. The floating gates of a plurality of transistors for generating different reference signal levels are connected in common so that the channel currents of all the transistors can be set simultaneously. The transistors have the channel lengths thereof, channel widths thereof, or both of them made different. The channel currents of the transistors are therefore mutually different. An error in all reference levels dependent on a manufacturing process is compensated for by adjusting an amount of charge to be injected into the floating gates.
摘要翻译：公开了一种技术，即使在用作输出多个不同的参考电平信号的参考单元电路中，即使用作参考单元的晶体管的数量并且每个具有浮动栅极的晶体管数量增加，也可能需要将沟道电流设置为晶体管不会增加。用于产生不同参考信号电平的多个晶体管的浮动栅极共同连接，使得可以同时设置所有晶体管的沟道电流。晶体管的沟道长度，沟道宽度或两者都不相同。因此，晶体管的沟道电流是相互不同的。依赖于制造过程的所有参考等级的误差通过调整要注入到浮动栅极的电荷量得到补偿。

14. 发明授权

US5469381A Semiconductor memory having non-volatile semiconductor memory cell 失效
标题翻译：具有非易失性半导体存储单元的半导体存储器
公开(公告)号：US5469381A
公开(公告)日：1995-11-21
申请号：US949236
申请日：1992-11-16
申请人： Hirokazu Yamazaki
发明人： Hirokazu Yamazaki
IPC分类号： G11C17/00 , G11C7/12 , G11C16/04 , G11C16/10 , G11C16/26 , G11C29/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C29/82 , G11C16/0441 , G11C16/10 , G11C16/26 , G11C7/12
摘要： A semiconductor memory having a non-volatile semiconductor memory cell, wherein the depletion of electrons from the semiconductor memory cell takes place in conjunction with the depletion of electrons from a load transistor so that a voltage difference between each threshold voltage can be maintained at the same level, and a writing operation is performed in a configuration where the load transistor of the non-volatile semiconductor memory cell is equipped with, like the non-volatile semiconductor memory cell, a floating gate, so that an initially stored memory content of the semiconductor memory cell can be read out.
摘要翻译： PCT No.PCT / JP92 / 00323 Sec。 371日期：1992年11月16日 102（e）日期1992年11月16日PCT 1991年3月18日PCT公布。第WO92 / 16946号公报日期：1992年1月10日。具有非易失性半导体存储单元的半导体存储器，其中来自半导体存储单元的电子的耗尽结合来自负载晶体管的电子的耗尽，使得每个阈值之间的电压差可以将电压维持在相同的电平，并且在非易失性半导体存储单元的负载晶体管像非易失性半导体存储单元一样配置浮动栅极的配置中进行写入操作，使得可以读出半导体存储单元的初始存储的存储器内容。

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