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11. 发明申请

US20170091120A1 Securing Writes to Memory Modules Having Memory Controllers 审中-公开
公开(公告)号：US20170091120A1
公开(公告)日：2017-03-30
申请号：US14865675
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/14 , G06F11/16 , G06F11/32
CPC分类号： G06F12/1408 , G06F11/1608 , G06F11/327 , G06F13/00 , G06F21/575 , G06F21/79 , G06F2212/1052
摘要： A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.

12. 发明授权

US09419792B2 Instruction for accelerating SNOW 3G wireless security algorithm 有权
标题翻译：加速SNOW 3G无线安全算法的指令
公开(公告)号：US09419792B2
公开(公告)日：2016-08-16
申请号：US13730216
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/00 , G06F7/00 , H04L9/06 , G09C1/00 , H04L29/06 , H04W12/02
CPC分类号： H04W12/02 , G06F9/30007 , G06F9/30036 , G06F9/30134 , G06F9/3887 , G09C1/00 , H04L9/065 , H04L9/0668 , H04L63/045 , H04L63/0457 , H04W12/04
摘要： Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
摘要翻译：用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。

13. 发明授权

US08874933B2 Instruction set for SHA1 round processing on 128-bit data paths 有权
标题翻译： 128位数据路径SHA1循环处理指令集
公开(公告)号：US08874933B2
公开(公告)日：2014-10-28
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

14. 发明授权

US08838997B2 Instruction set for message scheduling of SHA256 algorithm 有权
标题翻译： SHA256算法消息调度指令集
公开(公告)号：US08838997B2
公开(公告)日：2014-09-16
申请号：US13631165
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译：处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

15. 发明申请

US20140195782A1 METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM 有权
标题翻译：用于处理SHA-2安全冲洗算法的方法和装置
公开(公告)号：US20140195782A1
公开(公告)日：2014-07-10
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
摘要翻译：处理器包括指令解码器，用于接收处理安全散列算法2（SHA-2）散列算法的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储SHA-2状态和第二操作数与第二存储位置相关联以存储多个消息和回合常数。处理器还包括执行单元，其耦合到指令解码器，以在由第一操作数和由第二操作数指定的多个消息和循环常数指定的SHA-2状态上执行SHA-2散列算法的一个或多个迭代，响应第一条指令。

16. 发明申请

US20140189368A1 INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY 有权
标题翻译：指示和逻辑提供SIMD安全冲击圆形功能
公开(公告)号：US20140189368A1
公开(公告)日：2014-07-03
申请号：US13731004
申请日：2012-12-29
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
IPC分类号： G06F21/60
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G06F15/8007 , G06F21/602 , G06F21/64
摘要： Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.
摘要翻译：说明和逻辑提供SIMD安全散列圆切片功能。一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分圆周运算，旋转设定部分旋转设定。处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

17. 发明申请

US20140095891A1 INSTRUCTION SET FOR SHA1 ROUND PROCESSING ON 128-BIT DATA PATHS 有权
标题翻译： 128位数据表上的SHA1加工指令集
公开(公告)号：US20140095891A1
公开(公告)日：2014-04-03
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

18. 发明申请

US20140019693A1 PARALLEL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单个数据缓冲器的并行处理
公开(公告)号：US20140019693A1
公开(公告)日：2014-01-16
申请号：US13631761
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的流片段到数据寄存器中，并行地对每个片段执行算法，并且在每个片段上合并执行算法的结果形成串行数据处理算法的输出。

19. 发明申请

US20140016774A1 INSTRUCTIONS TO PERFORM GROESTL HASHING 有权
标题翻译：执行GROESTL HASHING的说明
公开(公告)号：US20140016774A1
公开(公告)日：2014-01-16
申请号：US13992461
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04L9/28
CPC分类号： H04L9/28 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F13/14 , H04L9/0631 , H04L9/0643
摘要： A method is described. The method includes executing an instruction to perform one or more Galois Field (GF) multiply by 2 operations on a state matrix and executing an instruction to combine results of the one or more GF multiply by 2 operations with exclusive or (XOR) functions to generate a result matrix.
摘要翻译：描述了一种方法。该方法包括执行在状态矩阵上乘以2次操作的一个或多个伽罗瓦域（GF）的指令，并且执行将所述一个或多个GF乘以2个运算的结果与异或（XOR）函数相结合的指令，以产生一个结果矩阵。

20. 发明申请

US20080240422A1 Efficient advanced encryption standard (AES) Datapath using hybrid rijndael S-Box 失效
标题翻译：高效的高级加密标准（AES）使用混合rijndael S-Box的数据路径
公开(公告)号：US20080240422A1
公开(公告)日：2008-10-02
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

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