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11. 发明授权

US5867045A Signal processor comprising means for holding output signals of image sensors and means for mixing the held signals 失效
标题翻译：信号处理器包括用于保持图像传感器的输出信号的装置和用于混合保持的信号的装置
公开(公告)号：US5867045A
公开(公告)日：1999-02-02
申请号：US744838
申请日：1996-11-19
申请人： Isamu Ueno , Mamoru Miyawaki , Tetsunobu Kohchi
发明人： Isamu Ueno , Mamoru Miyawaki , Tetsunobu Kohchi
IPC分类号： H04N5/347 , H04N5/369 , G11C27/02
CPC分类号： H04N3/1512 , H04N3/155
摘要： A signal processor with a simplified circuit configuration provides an improved processing speed and can be realized of small size and at inexpensive cost. The signal processor includes signal holding means for holding output signals from plural signal sources (S1-S4), and signal mixing means (M31-M34) for mixing at least two signals among the plural signals held to output plural mixed signals. Since the mixed signals are less than the signal sources in number, the small number of signal lines can lead to an increased processing speed. Then the mixed signals corresponding to discrete signals from plural signal sources enables processing without substantially destroying information.
摘要翻译：具有简化的电路配置的信号处理器提供了改进的处理速度，并且可以以小尺寸和廉价的成本实现。信号处理器包括用于保持来自多个信号源（S1-S4）的输出信号的信号保持装置和用于混合保持以输出多个混合信号的多个信号中的至少两个信号的信号混合装置（M31-M34）。由于混合信号的数量少于信号源，所以信号线的数量少可能导致处理速度的提高。那么对应于来自多个信号源的离散信号的混合信号使得能够进行处理而基本上不破坏信息。

12. 发明授权

US5567962A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5567962A
公开(公告)日：1996-10-22
申请号：US263147
申请日：1994-06-21
申请人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
发明人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/102 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/786 , H01L29/78
CPC分类号： H01L29/7851 , H01L21/823475 , H01L27/1026 , H01L27/10805 , H01L27/115 , H01L29/66795
摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
摘要翻译：一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上，绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

13. 发明授权

US6081825A Semiconductor device, semiconductor circuit using the device, and correlation calculation device, signal converter, and signal processing system using the circuit 失效
标题翻译：半导体器件，使用该器件的半导体电路，以及使用该电路的相关计算装置，信号转换器和信号处理系统
公开(公告)号：US6081825A
公开(公告)日：2000-06-27
申请号：US592571
申请日：1996-01-26
申请人： Tetsunobu Kohchi , Mamoru Miyawaki
发明人： Tetsunobu Kohchi , Mamoru Miyawaki
IPC分类号： H03M1/38 , G06F7/00 , G06F7/02 , G06F17/15 , G06J1/00 , G06T7/20 , G11C27/02 , H03K19/23 , H03M1/40 , H03M1/80 , G06G7/00
CPC分类号： H03K19/23 , G06F17/15 , G06F7/00 , G06F7/02 , G06J1/00 , G06T7/2013 , H03M1/403 , G06F2207/025 , G06T2207/10016 , H03M1/804
摘要： In a semiconductor device in which one terminal of each of plural capacitors is connected to a corresponding multiple input terminal via a switch, and the other terminals of the capacitors are commonly connected to a sense amplifier, the other terminal of at least one capacitor is commonly connected to the sense amplifier via a second switch, thereby reducing circuit scale, increasing operation speed, improving operation precision, and saving power.
摘要翻译：在多个电容器中的每一个的一个端子经由开关连接到对应的多个输入端子并且电容器的另一个端子共同连接到读出放大器的半导体器件中，至少一个电容器的另一个端子通常是通过第二开关连接到读出放大器，从而减小电路规模，提高运算速度，提高运算精度，节省功耗。

14. 发明授权

US5595920A Method of manufacturing a semiconductor memory device for use with image pickup 失效
标题翻译：制造用于图像拾取的半导体存储器件的方法
公开(公告)号：US5595920A
公开(公告)日：1997-01-21
申请号：US417831
申请日：1995-04-06
申请人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
发明人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/102 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/7851 , H01L21/823475 , H01L27/1026 , H01L27/10805 , H01L27/115 , H01L29/66795
摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
摘要翻译：一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上，绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

15. 发明授权

US5783842A Semiconductor device having an insulating layer having a concave section formed by oxidizing a semiconductor layer 失效
标题翻译：具有通过氧化半导体层而形成有凹部的绝缘层的半导体装置
公开(公告)号：US5783842A
公开(公告)日：1998-07-21
申请号：US803499
申请日：1997-02-20
申请人： Tetsunobu Kohchi , Mamoru Miyawaki
发明人： Tetsunobu Kohchi , Mamoru Miyawaki
IPC分类号： G02F1/1343 , G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/3205 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/04
CPC分类号： H01L27/12 , G02F1/1362
摘要： In a semiconductor device in which a passive element and an active element are formed on a substrate in which a thin film semiconductor layer is formed on an insulating layer or an insulating substrate, the device has a concave portion in at least a part of a portion below a wiring connecting the passive element or the active element.
摘要翻译：在其中在绝缘层或绝缘基板上形成有薄膜半导体层的基板上形成无源元件和有源元件的半导体器件中，该器件在部分的至少一部分中具有凹部在连接无源元件或有源元件的布线下面。

16. 发明授权

US5331197A Semiconductor memory device including gate electrode sandwiching a channel region 失效
标题翻译：半导体存储器件包括夹着沟道区的栅电极
公开(公告)号：US5331197A
公开(公告)日：1994-07-19
申请号：US870258
申请日：1992-04-17
申请人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
发明人： Mamoru Miyawaki , Akira Ishizaki , Genzo Momma , Hiroshi Yuzurihara , Tetsunobu Kohchi
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/102 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/786 , H01L29/78
CPC分类号： H01L29/7851 , H01L21/823475 , H01L27/1026 , H01L27/10805 , H01L27/115 , H01L29/66795
摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
摘要翻译：一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上，绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

17. 发明授权

US5994757A Electronic circuit device capable for use as a memory device 失效
标题翻译：能用作存储装置的电子电路装置
公开(公告)号：US5994757A
公开(公告)日：1999-11-30
申请号：US383186
申请日：1995-02-03
申请人： Takeshi Ichikawa , Mamoru Miyawaki , Shunsuke Inoue
发明人： Takeshi Ichikawa , Mamoru Miyawaki , Shunsuke Inoue
IPC分类号： G11C17/06 , G11C17/16 , H01L23/525 , H01L27/10 , H01L29/00 , H01L29/04 , H01L29/861
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002
摘要： An electronic circuit device includes first and second conductors and a high-resistance member arranged therebetween. The high-resistance member consists of a material which changes from a high resistivity state to a low resistivity state in accordance with a voltage applied between the first and second conductors.
摘要翻译：电子电路装置包括第一和第二导体以及设置在它们之间的高电阻部件。高电阻部件由根据施加在第一和第二导体之间的电压从高电阻率状态变为低电阻率状态的材料构成。

18. 发明授权

US5812231A Display unit 失效
标题翻译：显示单元
公开(公告)号：US5812231A
公开(公告)日：1998-09-22
申请号：US492247
申请日：1995-06-19
申请人： Tetsunobu Kochi , Mamoru Miyawaki , Shunsuke Inoue , Takanori Watanabe
发明人： Tetsunobu Kochi , Mamoru Miyawaki , Shunsuke Inoue , Takanori Watanabe
IPC分类号： G02F1/1333 , G02F1/133 , G02F1/1345 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/30 , G09G3/20 , G09G3/36 , H01L27/12 , H01L27/13 , H01L29/786 , G09G5/00 , H01L29/04
CPC分类号： G09G3/3688 , G09G3/3648 , H01L27/1203 , H01L27/13 , G02F1/13454 , G02F2001/136281 , G09G2310/0248 , G09G2310/0297 , G09G3/2011
摘要： A high-density impurity semiconductor region having the same conductivity type as a single-crystal silicon substrate is formed in addition to a main circuit portion of a peripheral circuit on the single-crystal silicon substrate. This semiconductor region is connected to a given potential point directly leading to an electric source. Alternatively, at a part of the peripheral drive circuit, a high-density impurity semiconductor region having a conductivity type reverse to that of the single-crystal silicon substrate is formed, and this semiconductor region is connected to a given potential point directly leading to an electric source. This can solve the problem that photocarriers (electrons and/or holes) caused by the light having not cut off and having entered into the single-crystal silicon region may enter into the peripheral drive circuit through the single-crystal silicon substrate to cause misoperation of the circuit.
摘要翻译：除了在单晶硅衬底上的外围电路的主电路部分之外，还形成具有与单晶硅衬底相同的导电类型的高密度杂质半导体区域。该半导体区域连接到直接通向电源的给定电位点。或者，在外围驱动电路的一部分，形成具有与单晶硅基板相反的导电类型的高密度杂质半导体区域，并且该半导体区域直接连接到给定的电位点，电源。这可以解决由未被切断并进入单晶硅区域的光引起的光载流子（电子和/或空穴）可能通过单晶硅衬底进入外围驱动电路的问题，导致误操作电路。

19. 发明授权

US5757054A Display unit 失效
标题翻译：显示单元
公开(公告)号：US5757054A
公开(公告)日：1998-05-26
申请号：US714439
申请日：1996-09-16
申请人： Mamoru Miyawaki , Shunsuke Inoue
发明人： Mamoru Miyawaki , Shunsuke Inoue
IPC分类号： G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/30 , H01L27/06 , H01L29/04 , H01L31/036
CPC分类号： G02F1/136277 , H01L27/0688 , G02F1/13454
摘要： The present invention solves problems as follows: a problem that, since light for displaying enters into a semiconductor substrate, carrier induced by light occurs in the semiconductor substrate, potential of the substrate fluctuates, and hence display characteristics become worse; a problem that, in the semiconductor substrate, voltages are applied to the peripheral driving circuits so as to operate the peripheral driving circuits formed in a single-crystal area, which makes display characteristics worse by the voltages being conducted to the display area through the substrate; and a problem that, in case potentials of adjacent pixels greatly differ, the difference locally changes. For this purpose, in a display unit including an active matrix substrate having an image display portion being provided with a plurality of switches and a driving circuit for supplying driving signals to the switches around the image display portion, an opposing substrate opposing the active matrix substrate and having a transparent electrode, and a liquid crystal material between both of the active matrix substrate and the opposing substrate, heavily doped impurity regions having impurity density heavier than that of the semiconductor substrate are formed in the image display portion, and the heavily doped impurity regions are connected to a fixed potential around the image display portion.
摘要翻译：本发明解决了以下问题：由于用于显示的光进入半导体衬底，所以在半导体衬底中产生由光引起的载流子，所以衬底的电位变动，因此显示特性变差; 在半导体基板中，向周边驱动电路施加电压以对形成在单晶区域中的外围驱动电路进行操作的问题在于，通过通过基板向显示区域传导的电压使显示特性变差 ; 以及在相邻像素的电位大大不同的情况下，差异局部变化的问题。为此，在包括具有图像显示部分的多个开关的有源矩阵基板和用于向图像显示部分周围的开关提供驱动信号的驱动电路的显示单元中，与有源矩阵基板相对的相对基板并且在有源矩阵基板和相对基板两者之间具有透明电极和液晶材料，在图像显示部分中形成具有比半导体基板重的杂质密度的重掺杂杂质区，并且重掺杂杂质区域连接到图像显示部分周围的固定电位。

20. 发明授权

US5412240A Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness 失效
标题翻译：绝缘体上硅CMOS器件和具有受控基极绝缘体厚度的液晶显示器
公开(公告)号：US5412240A
公开(公告)日：1995-05-02
申请号：US274156
申请日：1994-07-14
申请人： Shunsuke Inoue , Toru Koizumi , Mamoru Miyawaki , Shigetoshi Sugawa
发明人： Shunsuke Inoue , Toru Koizumi , Mamoru Miyawaki , Shigetoshi Sugawa
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/208 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/01 , H01L27/13
CPC分类号： H01L27/1203
摘要： A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation:T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1where K.sub.1 .tbd..epsilon..sub.BOX (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd.2.PHI..sub.FN +2.PHI..sub.FP -1.03, .epsilon..sub.BOX.sup.-1 is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .PHI..sub.FN and .PHI..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.
摘要翻译：半导体器件具有形成在形成在绝缘层上的薄膜Si层中形成的至少一个单晶Si区上的NMOS晶体管和PMOS晶体管。形成NMOS和PMOS晶体管的绝缘层的厚度TBOX，低压电源的电压VSS和NMOS和PMOS晶体管的高压电源的电压VDD满足由以下等式：TBOX>（VDD-VSS-K2）/ K1其中K1 3BONDεBOX（QBN + QBP），K2 3BOND 2 PHI FN + 2 PHI FP-1.03，εBOX-1是基础绝缘层的介电常数当NMOS和PMOS晶体管的耗尽层的宽度最大化时，QBN和QBP是体电荷，而PHI FN和PHI FP是NMOS和PMOS晶体管的伪费米电位。

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