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11. 发明授权

US5020029A Static semiconductor memory device with predetermined threshold voltages 失效
标题翻译：具有预定阈值电压的静态半导体存储器件
公开(公告)号：US5020029A
公开(公告)日：1991-05-28
申请号：US547263
申请日：1990-07-03
申请人： Katsuki Ichinose , Tomohisa Wada
发明人： Katsuki Ichinose , Tomohisa Wada
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , Y10S257/903
摘要： A high resistance/load type memory cell of a static semiconductor memory device includes two load elements, two driver transistors, and two access transistors. The threshold voltage of each driver transistor is set at a high value so that the OFF resistance value of the driver transistor is 10 to 100 times the resistance value of each load resistance. The threshold voltage of each access transistor is set to be lower than the threshold voltage of each driver transistor so that the OFF resistance value of the access transistor is twice to 10 times the resistance value of each load resistance. Thus, power consumption in a standby state is reduced, while data holding characteristics of the memory cell are stabilized in selected and non-selected states.
摘要翻译：静态半导体存储器件的高电阻/负载型存储单元包括两个负载元件，两个驱动晶体管和两个存取晶体管。每个驱动晶体管的阈值电压被设置为高值，使得驱动晶体管的截止电阻值为每个负载电阻的电阻值的10至100倍。每个存取晶体管的阈值电压被设置为低于每个驱动晶体管的阈值电压，使得存取晶体管的截止电阻值是每个负载电阻的电阻值的两倍至十倍。因此，在备用状态下的功耗被降低，而存储单元的数据保持特性在选定状态和非选择状态下稳定。

12. 发明授权

US4645998A Constant voltage generating circuit 失效
标题翻译：恒压发生电路
公开(公告)号：US4645998A
公开(公告)日：1987-02-24
申请号：US770426
申请日：1985-08-29
申请人： Hirofumi Shinohara , Katsuki Ichinose
发明人： Hirofumi Shinohara , Katsuki Ichinose
IPC分类号： G05F3/24 , G05F3/20
CPC分类号： G05F3/247
摘要： A constant voltage generating circuit comprises a power supply terminal (1), an output terminal (2), a p-channel MOS FET (3), n-channel MOS FET's (4 and 5) and resistors (8 and 9). A node C of the resistors (8) and (9) is connected to a control terminal of the n-channel MOS FET (4), whereby the potential in the output terminal (2) is determined mainly by the threshold voltage of the n-channel MOS FETs (4) and (5), a ratio of the resistance values of the resistors (8) and (9) and a degree of conduction of the n-channel MOS FET (4). Instead of the resistors (8) and (9), n-channel MOS FET's (10 and 11) may be provided so as to compensate for the influence of power supply voltage in the output voltage by changing the impedance of the n-channel MOS FET (10) according to the change of the voltage of the power supply terminal (1).
摘要翻译：恒压生成电路包括电源端子（1），输出端子（2），p沟道MOS FET（3），n沟道MOS FET（4和5）和电阻器（8和9）。电阻器（8）和（9）的节点C连接到n沟道MOS FET（4）的控制端子，由此输出端子（2）中的电位主要由n的阈值电压沟道MOS FET（4）和（5），电阻器（8）和（9）的电阻值与n沟道MOS FET（4）的导通率之比。代替电阻器（8）和（9），可以提供n沟道MOS FET（10和11），以通过改变n沟道MOS的阻抗来补偿输出电压中的电源电压的影响 FET（10）根据电源端子（1）的电压变化。

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