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11. 发明申请

US20090180225A1 ESD PROTECTION STRUCTURE 有权
标题翻译： ESD保护结构
公开(公告)号：US20090180225A1
公开(公告)日：2009-07-16
申请号：US12191179
申请日：2008-08-13
申请人： Chi-Liang Pan , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chen-Hsuan Chiu
发明人： Chi-Liang Pan , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chen-Hsuan Chiu
IPC分类号： H02H9/00
CPC分类号： H01L23/60 , H01L2224/16225 , H01L2224/48091 , H01L2924/15311 , H01L2924/3011 , H05K1/0257 , H05K1/0259 , H05K1/0373 , H05K1/116 , H05K1/167 , H05K3/4688 , H05K2201/0738 , H05K2201/09718 , H01L2924/00014
摘要： An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.
摘要翻译：提供ESD保护结构。衬底包括第一电压可变材料，并具有第一表面，与第一表面基本平行的第二表面和连接第一表面和第二表面的通孔。第一金属层设置在衬底中用于耦合到接地端子。当ESD事件发生时，第一电压可变材料处于导通状态，使得通孔与第一金属层电连接以形成放电路径，并且当ESD事件为ESD时，第一电压可变材料处于隔离状态不存在，使得通孔与第一金属层电隔离。

12. 发明授权

US07894172B2 ESD protection structure 有权
标题翻译： ESD保护结构
公开(公告)号：US07894172B2
公开(公告)日：2011-02-22
申请号：US12191179
申请日：2008-08-13
申请人： Chi-Liang Pan , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chen-Hsuan Chiu
发明人： Chi-Liang Pan , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chen-Hsuan Chiu
IPC分类号： H05F3/00
CPC分类号： H01L23/60 , H01L2224/16225 , H01L2224/48091 , H01L2924/15311 , H01L2924/3011 , H05K1/0257 , H05K1/0259 , H05K1/0373 , H05K1/116 , H05K1/167 , H05K3/4688 , H05K2201/0738 , H05K2201/09718 , H01L2924/00014
摘要： An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.
摘要翻译：提供ESD保护结构。衬底包括第一电压可变材料，并具有第一表面，与第一表面基本平行的第二表面和连接第一表面和第二表面的通孔。第一金属层设置在衬底中用于耦合到接地端子。当ESD事件发生时，第一电压可变材料处于导通状态，使得通孔与第一金属层电连接以形成放电路径，并且当ESD事件为ESD时，第一电压可变材料处于隔离状态不存在，使得通孔与第一金属层电隔离。

13. 发明申请

US20090107717A1 ELECTRICALLY CONDUCTIVE STRUCTURE OF CIRCUIT BOARD AND CIRCUIT BOARD USING THE SAME 有权
标题翻译：使用电路板和电路板的电导体结构
公开(公告)号：US20090107717A1
公开(公告)日：2009-04-30
申请号：US12181330
申请日：2008-07-29
申请人： Chien-Min Hsu , Shih-Hsien Wu , Shinn-Juh LAI , Min-Lin LEE
发明人： Chien-Min Hsu , Shih-Hsien Wu , Shinn-Juh LAI , Min-Lin LEE
IPC分类号： H05K1/11
CPC分类号： H05K1/112 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0228 , H05K1/0231 , H05K1/0263 , H05K1/162 , H05K1/185 , H05K3/429 , H05K3/4602 , H05K2201/09245 , H05K2201/09627 , H05K2201/09709 , H05K2201/10734 , H01L2224/05599
摘要： An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.
摘要翻译：导电结构包括第一导电结构和第二导电结构。每个在一端具有导电部分，另一端具有耦合部分。第一和第二导电部分分别电连接到电子设备的电源和接地触点。第一和第二耦合部分分别与电路板的电源层和接地层连接。第一耦合部分通过第一延伸部分与第一导电部分连接，第二耦合部分通过第二延伸部分与第二导电部分连接。导电结构的至少两个耦合部分成对布置。第一导电结构和第二导电结构以交错阵列布置以形成具有相反电流方向的两个布线环，从而产生磁通消除效果。

14. 发明申请

US20090097175A1 ESD PROTECTION SUBSTRATE AND INTEGRATED CIRCUIT UTILIZING THE SAME 有权
标题翻译： ESD保护基板和整合电路
公开(公告)号：US20090097175A1
公开(公告)日：2009-04-16
申请号：US12047283
申请日：2008-03-12
申请人： Chen-Hsuan Chiu , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chi-Liang Pan
发明人： Chen-Hsuan Chiu , Min-Lin Lee , Shinn-Juh Lai , Shih-Hsien Wu , Chi-Liang Pan
IPC分类号： H02H9/00 , H01L27/02
CPC分类号： H01L23/60 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/49171 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.
摘要翻译：公开了ESD保护衬底。 ESD保护衬底包括第一导体，第二导体，尖锐结构和ESD保护材料。尖的结构电连接到第一或第二导体。 ESD保护材料设置在第一和第二导体之间。

15. 发明授权

US07893359B2 Embedded capacitor core having a multiple-layer structure 有权
标题翻译：具有多层结构的嵌入式电容器芯
公开(公告)号：US07893359B2
公开(公告)日：2011-02-22
申请号：US11470435
申请日：2006-09-06
申请人： Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay , Chih-Hao Chang
发明人： Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay , Chih-Hao Chang
IPC分类号： H05K1/16 , H05K1/18
CPC分类号： H05K1/162 , H05K3/4611 , H05K2201/0209 , H05K2201/09309 , Y10T29/43 , Y10T29/49126
摘要： An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.
摘要翻译：一种嵌入式电容器芯，包括第一组电容器，第二组电容器和在第一组电容器和第二组电容器之间的层间电介质膜。第一组电容器包括：包括至少两个导电电极的第一导电图案; 第二导电图案，包括对应于第一导电图案的两个导电电极的至少两个导电电极; 以及在第一导电图案和第二导电图案之间的第一电介质膜。第二组电容器包括：包括至少两个导电电极的第三导电图案; 第四导电图案，包括对应于第三导电图案的两个导电电极的至少两个导电电极; 以及在第三导电图案和第四导电图案之间的第二电介质膜。

16. 发明申请

US20070164395A1 CHIP PACKAGE WITH BUILT-IN CAPACITOR STRUCTURE 审中-公开
标题翻译：具有内置电容结构的芯片封装
公开(公告)号：US20070164395A1
公开(公告)日：2007-07-19
申请号：US11308493
申请日：2006-03-30
申请人： Jiin-Shing Perng , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
发明人： Jiin-Shing Perng , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
IPC分类号： H01L29/00
CPC分类号： H01L23/642 , H01L23/13 , H01L23/3107 , H01L23/4951 , H01L23/49589 , H01L23/49816 , H01L23/49822 , H01L24/48 , H01L24/49 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/49109 , H01L2224/4911 , H01L2224/73215 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the first metal foil and the second metal foil. The carrier is disposed on the surface away from the dielectric layer of the second metal foil. The first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil. The molding compound is disposed on the carrier for fixing the IC unit, the capacitor unit and the carrier.
摘要翻译：提供具有集成电路（IC）单元，电容器单元，载体和模塑料的内置电容器结构的芯片封装。电容器单元设置在IC单元上，并且包括第一金属箔，第二金属箔和设置在第一金属箔和第二金属箔之间的电介质层。载体设置在远离第二金属箔的电介质层的表面上。第一金属箔与载体电连接，第二金属箔电连接到载体上，IC单元与载体电连接，IC单元电连接到第一金属箔，并且IC单元电气连接到第二金属箔。模制化合物设置在载体上用于固定IC单元，电容器单元和载体。

17. 发明申请

US20060285273A1 Composite distributed dielectric structure 失效
标题翻译：复合分布介质结构
公开(公告)号：US20060285273A1
公开(公告)日：2006-12-21
申请号：US11156350
申请日：2005-06-17
申请人： Chih-Hao Chang , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
发明人： Chih-Hao Chang , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
IPC分类号： H01G4/20
CPC分类号： H05K1/024 , H01L23/49822 , H01L2924/0002 , H01L2924/3011 , H01P3/081 , H01P3/085 , H05K1/0298 , H05K3/386 , H05K2201/0187 , H05K2201/0195 , H05K2201/09881 , H01L2924/00
摘要： This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.
摘要翻译：本发明公开了一种复合分布介质结构。它包括一个或多个导体层，分布在导体层上的一个或多个电介质层，以及分布在电介质层上的一个或多个导体迹线。一个或多个电介质板可以进一步围绕导体迹线。在两个实施例中分别描述了介电层或板可以具有或可以不具有多个电介质材料。每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。两个或多个电介质层可以堆叠在导体层上本发明为互连系统提供了一种低成本和实用的电介质结构，以减少介质损耗，串扰和信号传播延迟，并且在保持适当的散热的同时良好地控制阻抗匹配，高频传输降噪。

18. 发明授权

US07349196B2 Composite distributed dielectric structure 失效
标题翻译：复合分布介质结构
公开(公告)号：US07349196B2
公开(公告)日：2008-03-25
申请号：US11156350
申请日：2005-06-17
申请人： Chih-Hao Chang , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
发明人： Chih-Hao Chang , Shih-Hsien Wu , Min-Lin Lee , Shinn-Juh Lay
IPC分类号： H01G4/06
CPC分类号： H05K1/024 , H01L23/49822 , H01L2924/0002 , H01L2924/3011 , H01P3/081 , H01P3/085 , H05K1/0298 , H05K3/386 , H05K2201/0187 , H05K2201/0195 , H05K2201/09881 , H01L2924/00
摘要： A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.
摘要翻译：复合分布介质结构包括一个或多个导体层，分布在导体层上的一个或多个电介质层和分布在电介质层上的一个或多个导体迹线。可以在导体迹线周围进一步形成一个或多个电介质板。介电层或板可以具有或可以不具有多个电介质材料。每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。可以在导体层上堆叠两个或更多个电介质层。

19. 发明申请

US20070187815A1 Encapsulation and methods thereof 有权
标题翻译：封装及其方法
公开(公告)号：US20070187815A1
公开(公告)日：2007-08-16
申请号：US11392721
申请日：2006-03-30
申请人： Ming-Ji Dai , Chun-Kai Liu , Chih-Kuang Yu , Shih-Hsien Wu
发明人： Ming-Ji Dai , Chun-Kai Liu , Chih-Kuang Yu , Shih-Hsien Wu
IPC分类号： H01L23/34
CPC分类号： H01L25/167 , H01L33/645 , H01L35/32 , H01L35/34 , H01L2224/48091 , H01L2224/85385 , H05K1/0203 , H01L2924/00014
摘要： The invention discloses an encapsulation comprising a metal substrate, a PCB on the metal substrate, a thermo-electric element in and/or on the PCB, and an LED on the thermo-electric element. Encapsulating methods are also provided by the invention.
摘要翻译：本发明公开了一种包括金属基底，金属基底上的PCB，PCB中和/或PCB上的热电元件以及热电元件上的LED的封装。封装方法也由本发明提供。

20. 发明授权

US08853848B2 Interconnection structure, apparatus therewith, circuit structure therewith 有权
标题翻译：互连结构，装置，其电路结构
公开(公告)号：US08853848B2
公开(公告)日：2014-10-07
申请号：US13109016
申请日：2011-05-17
申请人： Shih-Hsien Wu
发明人： Shih-Hsien Wu
IPC分类号： H01L23/48 , H01L23/14 , H05K1/02 , H01L21/768 , H01L21/48 , H01L23/498
CPC分类号： H05K1/0222 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2924/0002 , H05K2201/096 , H01L2924/00
摘要： An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.
摘要翻译：互连结构设置在基本上彼此平行的第一导电层和第二导电层之间。导电层包括信号迹线。互连结构包括导体柱和屏蔽壁支柱。导体柱通过两个导电层之间并与第一导电层的信号迹线电连接。屏蔽壁柱也设置在两个导电层之间并且位于围绕导体柱的外部区域的一部分并且电耦合到导体柱。导体柱和屏蔽壁支柱成对或组合配置。具有与导体柱不同的形状的屏蔽壁支柱将导致导体柱与设计阻抗的连接以及基于其特殊形状设计来控制阻抗的能力。

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