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11. 外观设计

USD400182S Motor controller 失效
公开(公告)号：USD400182S
公开(公告)日：1998-10-27
申请号：US78466
申请日：1997-10-27
申请人： Shigekazu Yamada
设计人： Shigekazu Yamada

12. 发明授权

US09159452B2 Automatic word line leakage measurement circuitry 有权
标题翻译：自动字线泄漏测量电路
公开(公告)号：US09159452B2
公开(公告)日：2015-10-13
申请号：US12271140
申请日：2008-11-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C29/02 , G11C16/04 , G11C29/12 , G11C29/50
CPC分类号： G11C7/1006 , G11C7/062 , G11C16/04 , G11C16/08 , G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.
摘要翻译：本发明是用于测量存储装置中的多条字线上的泄漏的电路和方法。在一个实施例中，存储器件可以包括耦合到存储器件的多个字线的泄漏测量电路。泄漏测量电路可以用于产生参考电流并且确定多个字线中的一个字线上的泄漏电流相对于参考电流是否可接受。在另一个实施例中，一种方法可以包括使用存储器件中的电路来确定存储器件的多个字线中的一个字线上的泄漏是否被允许。

13. 发明授权

US08482986B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US08482986B2
公开(公告)日：2013-07-09
申请号：US13550241
申请日：2012-07-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

14. 发明申请

US20130003464A1 CIRCUITS, SYSTEMS, AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中驱动位线上的高电压和低电压的电路，系统和方法
公开(公告)号：US20130003464A1
公开(公告)日：2013-01-03
申请号：US13610512
申请日：2012-09-11
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的过程或温度变化而变化过程或温度变化。

15. 发明申请

US20120218833A1 LEAKAGE MEASUREMENT SYSTEMS 有权
标题翻译：泄漏测量系统
公开(公告)号：US20120218833A1
公开(公告)日：2012-08-30
申请号：US13036409
申请日：2011-02-28
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/06 , G11C16/00 , G11C16/0483 , G11C29/025 , G11C29/50008 , G11C2029/1202 , G11C2029/5006
摘要： Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.
摘要翻译：所描述的示例包括泄漏测量系统和用于测量升压电压的字线与电源电压下的字线之间的漏电流的方法。升压电压可能由电荷泵电路产生。这里描述的泄漏测量系统的示例可以包括在存储器设备中。

16. 发明授权

US08194446B2 Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage 有权
标题翻译：使用小于电源电压的禁止电压对存储器件和存储器件进行编程的方法
公开(公告)号：US08194446B2
公开(公告)日：2012-06-05
申请号：US13051380
申请日：2011-03-18
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0433
摘要： Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.
摘要翻译：公开了用于编程存储器阵列和存储器件的方法。在一种这样的方法中，禁止的位线被充电到小于电源电压的抑制电压。要编程的存储器单元的字线被偏置在比常规技术中使用的小于标称编程准备电压的编程准备电压。当非禁止位线为0V时，编程脉冲可以施加到要编程的存储单元的选定字线。

17. 发明申请

US20110249503A1 SELECT GATE PROGRAMMING IN A MEMORY DEVICE 有权
标题翻译：在存储器中选择编程
公开(公告)号：US20110249503A1
公开(公告)日：2011-10-13
申请号：US12756366
申请日：2010-04-08
申请人： Shigekazu Yamada , Aaron Yip
发明人： Shigekazu Yamada , Aaron Yip
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C16/102 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
摘要翻译：公开了用于编程选择门，存储器件和存储器系统的方法。在一种用于编程的方法中，程序禁止电压从源极线传送到未选位线。在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

18. 发明授权

US07872920B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US07872920B2
公开(公告)日：2011-01-18
申请号：US12572957
申请日：2009-10-02
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

19. 发明申请

US20100220530A1 CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中驱动位线上的高电压和低电压的电路，系统和方法
公开(公告)号：US20100220530A1
公开(公告)日：2010-09-02
申请号：US12780594
申请日：2010-05-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的过程或温度变化而变化过程或温度变化。

20. 发明授权

US07768817B2 VCC control inside data register of memory device 有权
标题翻译：内存数据寄存器内的VCC控制
公开(公告)号：US07768817B2
公开(公告)日：2010-08-03
申请号：US12052271
申请日：2008-03-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/00
CPC分类号： G11C5/147
摘要： A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.
摘要翻译：提供了一种包括耦合到数据寄存器内的第一反相器的限流电路的存储器件。限流电路控制提供给第一反相器的电压，并且可以调整参考电压，使得防止提供给第一反相器的电压降到低于提供给数据寄存器内的第二反相器的电压。存储器件可以包括开关，以允许耦合到限流电路以编程存储器件。

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