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11. 发明申请

US20090278173A1 MEMORY DEVICE INTERCONNECTS AND METHOD OF MANUFACTURING 有权
标题翻译：存储器件互连和制造方法
公开(公告)号：US20090278173A1
公开(公告)日：2009-11-12
申请号：US12116200
申请日：2008-05-06
申请人： Shenqing FANG , Connie WANG , Wen YU , Fei WANG
发明人： Shenqing FANG , Connie WANG , Wen YU , Fei WANG
IPC分类号： H01L29/66 , H01L21/4763
CPC分类号： H01L23/528 , H01L21/76807 , H01L21/76813 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
摘要翻译：在一个实施例中，集成电路存储器件包括具有多个位线的衬底。第一和第二层间电介质层依次设置在基板上。多个源极线和交错位线触点中的每一个延伸穿过第一层间电介质层。多个源极线路通孔和多个交错位线通孔中的每一条通过第二级间介电层延伸到多条源极线路和多条交错位线触点中的每一个。通过第一组制造工艺一起形成延伸穿过第一层间电介质层的源极线和交错位线触点。延伸穿过第二层间电介质层的源极线通孔和交错位线触点也通过第二组制造工艺一起形成。

12. 发明申请

US20120156856A1 PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS 有权
标题翻译：电荷捕捉场效应晶体管中的工艺工程
公开(公告)号：US20120156856A1
公开(公告)日：2012-06-21
申请号：US12973631
申请日：2010-12-20
申请人： Tung-Sheng CHEN , Shenqing FANG
发明人： Tung-Sheng CHEN , Shenqing FANG
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/28282 , H01L27/1157 , H01L29/792
摘要： Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.
摘要翻译：本技术的实施例针对电荷捕获场效应晶体管的电荷捕获区域工艺裕度工程。这些技术包括在衬底上形成多个浅沟槽隔离区域，其中浅沟槽隔离区域的顶部在衬底上延伸给定量。衬底的一部分被氧化以形成隧道电介质区域。第一组一个或多个氮化物层沉积在隧道电介质区域和浅沟槽隔离区域上，其中第一组氮化物层的厚度大约为给定量的一半，即浅沟槽隔离区的顶部在上面延伸底物。第一组氮化物层的一部分被回蚀刻到沟槽隔离区的顶部。在蚀刻后的第一组氮化物层上沉积第二组一个或多个氮化物层。第二组氮化物层被氧化以在隧穿电介质区域上形成电荷俘获区域，并在电荷俘获区域上形成阻挡电介质区域。然后将栅极区域沉积在阻挡电介质区域上。

13. 发明申请

US20120153377A1 EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING 有权
标题翻译：边缘圆形场效应晶体管及其制造方法
公开(公告)号：US20120153377A1
公开(公告)日：2012-06-21
申请号：US12973756
申请日：2010-12-20
申请人： Shenqing FANG , Tung-Sheng CHEN
发明人： Shenqing FANG , Tung-Sheng CHEN
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28202 , H01L27/11568 , H01L29/518
摘要： Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.
摘要翻译：本技术的实施例针对场效应晶体管的栅极侧壁工程。这些技术包括形成阻挡电介质区域和其表面的氮化。在阻挡电介质区域的氮化之后，在其上形成栅极区域，并且栅极区域的侧壁被氧化以围绕栅极尖锐拐角并减小栅极拐角处的电场。

14. 发明申请

US20110272775A1 3D INTEGRATED CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译： 3D集成电路系统和方法
公开(公告)号：US20110272775A1
公开(公告)日：2011-11-10
申请号：US13183373
申请日：2011-07-14
申请人： Eunha KIM , Jeremy WAHL , Shenqing FANG , YouSeok SUH , Kuo-Tung CHANG , Yi MA , Rinji SUGINO , Jean YANG
发明人： Eunha KIM , Jeremy WAHL , Shenqing FANG , YouSeok SUH , Kuo-Tung CHANG , Yi MA , Rinji SUGINO , Jean YANG
IPC分类号： H01L29/02
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译：提出了半导体制造系统和方法。三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

15. 发明申请

US20100065940A1 3-D INTEGRATED CIRCUIT SYSTEM AND METHOD 有权
标题翻译： 3-D集成电路系统及方法
公开(公告)号：US20100065940A1
公开(公告)日：2010-03-18
申请号：US12209478
申请日：2008-09-12
申请人： Eunha KIM , Jeremy WAHL , Shenqing FANG , YouSeok SUH , Kuo-Tung CHANG , Yi MA , Rinji SUGINO , Jean YANG
发明人： Eunha KIM , Jeremy WAHL , Shenqing FANG , YouSeok SUH , Kuo-Tung CHANG , Yi MA , Rinji SUGINO , Jean YANG
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译：提出了半导体制造系统和方法。三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

16. 发明申请

US20140001534A1 APPARATUS AND METHOD FOR ROUNDED ONO FORMATION IN A FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件中的圆形形成装置和方法
公开(公告)号：US20140001534A1
公开(公告)日：2014-01-02
申请号：US13540373
申请日：2012-07-02
申请人： Shenqing FANG , Tung-Sheng CHEN , Tim THURGATE , Di LI
发明人： Shenqing FANG , Tung-Sheng CHEN , Tim THURGATE , Di LI
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L21/28282 , H01L21/76224 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
摘要翻译：一种用于在闪速存储器件中连续成形的电荷俘获层形成的方法和装置。存储器件包括包括源/漏区的半导体层。隔离区域邻近源极/漏极区域设置。第一绝缘体设置在源极/漏极区域的上方。电荷捕获层设置在第一绝缘体内，其中电荷捕获层包括主体部分和在所述主体部分的任一侧上的第一尖端和第二尖端，其中所述电荷捕获层延伸超过源极/漏极的宽度地区。第二绝缘体设置在电荷捕获层上方。多晶硅栅极结构设置在第二绝缘体上方，其中所述控制栅极的宽度比所述源极/漏极区域的宽度宽。

17. 发明申请

US20120156876A1 SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING 有权
标题翻译：自对准NAND闪存选择门字幕用于双面格式
公开(公告)号：US20120156876A1
公开(公告)日：2012-06-21
申请号：US12971818
申请日：2010-12-17
申请人： Tung-Sheng CHEN , Shenqing FANG
发明人： Tung-Sheng CHEN , Shenqing FANG
IPC分类号： H01L21/306
CPC分类号： H01L21/302 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
摘要翻译：公开了一种用于双重图案化的方法。在一个实施例中，通过在光致抗蚀剂图案的边缘周围放置间隔图案来开始在多个核心字线的任一侧上形成一对选择栅极字线。将光致抗蚀剂图案剥离留下间隔图案。修剪掩模放置在间隔图案的一部分上。间隔图案的部分被蚀刻掉，不被修剪掩模覆盖。去除修剪掩模，其中间隔图案的第一剩余部分限定多个核心字线。放置焊盘掩模，使得焊盘掩模和间隔物图案的第二剩余部分在多个核心字线的任一侧上限定选择栅极字线。最后，通过使用激光掩模和间隔物图案的第一和第二剩余部分来蚀刻至少一个图案转印层，以将选择栅极字线和多个核心字线蚀刻成多晶硅层。

18. 发明申请

US20110013449A1 SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS 有权
公开(公告)号：US20110013449A1
公开(公告)日：2011-01-20
申请号：US12891532
申请日：2010-09-27
申请人： Shenqing FANG , Kuo-Tung CHANG , Tim THURGATE , YouSeok SUH , Allison HOLBROOK
发明人： Shenqing FANG , Kuo-Tung CHANG , Tim THURGATE , YouSeok SUH , Allison HOLBROOK
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

19. 发明申请

US20100085811A1 SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME 有权
标题翻译： NAND FLASH MEMORY CELL STRING的缩放选择门及其形成方法
公开(公告)号：US20100085811A1
公开(公告)日：2010-04-08
申请号：US12246981
申请日：2008-10-07
申请人： YouSeok SUH , Shenqing FANG , Kuo-Tung CHANG
发明人： YouSeok SUH , Shenqing FANG , Kuo-Tung CHANG
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483
摘要： A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.
摘要翻译：具有按比例缩小的选择门的NAND快闪存储器单元串。 NAND闪存单元串包括具有140nm或更小的宽度的第一选择栅极和耦合到第一选择栅极的多个字线。与多个字线相关联的门由p +多晶硅形成。具有140nm或更小的宽度的第二选择栅极耦合到多个字线。

20. 发明申请

US20090261406A1 USE OF SILICON-RICH NITRIDE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：在闪存存储器件中使用富含硅的硝酸盐
公开(公告)号：US20090261406A1
公开(公告)日：2009-10-22
申请号：US12105208
申请日：2008-04-17
申请人： Youseok SUH , Shenqing FANG , Kuo Tung CHANG , Rinji SUGINO , Yi MA , Eunha KIM
发明人： Youseok SUH , Shenqing FANG , Kuo Tung CHANG , Rinji SUGINO , Yi MA , Eunha KIM
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/513 , H01L29/7882
摘要： A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio of silicon-to-nitrogen in the second layer.
摘要翻译：闪存单元包括至少包括第一层和第二层的电荷存储元件。其中一层包括富含硅的氮化硅，另一层包括氮化硅。更具体地说，第一层中硅与氮的比例大于第二层中硅与氮的比例。

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